1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Meraki MR33 (Stinkbug)
5 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
6 * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
8 * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
15 #include "qcom-ipq4019.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/soc/qcom,tcsr.h>
21 model = "Meraki MR33 Access Point";
22 compatible = "meraki,mr33";
25 led-boot = &status_green;
26 led-failsafe = &status_red;
27 led-running = &status_green;
28 led-upgrade = &power_orange;
31 /* Do we really need this defined? */
33 device_type = "memory";
34 reg = <0x80000000 0x10000000>;
44 pinctrl-0 = <&mdio_pins>;
45 pinctrl-names = "default";
48 /* It is a 56-bit counter that supplies the count to the ARM arch
49 timers and without upstream driver */
51 compatible = "qcom,qca-gcnt";
56 compatible = "qcom,tcsr";
57 reg = <0x1953000 0x1000>;
58 qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
62 compatible = "qcom,tcsr";
63 reg = <0x1949000 0x100>;
64 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
68 compatible = "qcom,tcsr";
69 reg = <0x1957000 0x100>;
70 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
74 pinctrl-0 = <&serial_1_pins>;
75 pinctrl-names = "default";
79 compatible = "ti,cc2650";
80 enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
93 switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
94 switch_lan_bmp = <0x0>; /* lan port bitmap */
95 switch_wan_bmp = <0x10>; /* wan port bitmap */
101 phy-mode = "rgmii-rxid";
107 compatible = "gpio-keys";
111 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
112 linux,code = <KEY_RESTART>;
117 compatible = "gpio-leds";
119 power_orange: power {
120 label = "mr33:orange:power";
121 gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
132 pinctrl-0 = <&serial_0_pins>;
133 pinctrl-names = "default";
142 qcom,phy_mdio_addr = <1>;
143 qcom,poll_required = <1>;
148 pinctrl-0 = <&i2c_0_pins>;
149 pinctrl-names = "default";
152 compatible = "atmel,24c64";
155 read-only; /* This holds our MAC & Meraki board-data */
160 pinctrl-0 = <&i2c_1_pins>;
161 pinctrl-names = "default";
165 compatible = "ti,lp5562";
167 clock-mode = /bits/8 <2>;
168 enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
172 chan-name = "mr33:red:status";
173 led-cur = /bits/ 8 <0x20>;
174 max-cur = /bits/ 8 <0x60>;
177 status_green: chan1 {
178 chan-name = "mr33:green:status";
179 led-cur = /bits/ 8 <0x20>;
180 max-cur = /bits/ 8 <0x60>;
184 chan-name = "mr33:blue:status";
185 led-cur = /bits/ 8 <0x20>;
186 max-cur = /bits/ 8 <0x60>;
190 chan-name = "mr33:white:status";
191 led-cur = /bits/ 8 <0x20>;
192 max-cur = /bits/ 8 <0x60>;
198 pinctrl-0 = <&nand_pins>;
199 pinctrl-names = "default";
204 compatible = "fixed-partitions";
205 #address-cells = <1>;
210 reg = <0x00000000 0x00100000>;
215 reg = <0x00100000 0x00100000>;
219 label = "bootconfig";
220 reg = <0x00200000 0x00100000>;
225 reg = <0x00300000 0x00100000>;
230 reg = <0x00400000 0x00100000>;
235 reg = <0x00500000 0x00080000>;
240 reg = <0x00580000 0x00080000>;
245 reg = <0x00600000 0x00080000>;
250 reg = <0x00700000 0x00200000>;
254 label = "u-boot-backup";
255 reg = <0x00900000 0x00200000>;
260 reg = <0x00b00000 0x00080000>;
265 reg = <0x00c00000 0x07000000>;
267 * Do not try to allocate the remaining
268 * 4 MiB to this ubi partition. It will
269 * confuse the u-boot and it might not
270 * find the kernel partition anymore.
279 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
280 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
283 reg = <0x00000000 0 0 0 0>;
284 #address-cells = <3>;
289 compatible = "qcom,ath10k";
291 reg = <0x00010000 0 0 0 0>;
302 * GPIO43 should be 0/1 whenever the unit is
303 * powered through PoE or AC-Adapter.
304 * That said, playing with this seems to
308 mdio_pins: mdio_pinmux {
321 serial_0_pins: serial_pinmux {
323 pins = "gpio16", "gpio17";
324 function = "blsp_uart0";
329 serial_1_pins: serial1_pinmux {
331 /* We use the i2c-0 pins for serial_1 */
332 pins = "gpio8", "gpio9";
333 function = "blsp_uart1";
338 i2c_0_pins: i2c_0_pinmux {
340 function = "blsp_i2c0";
341 pins = "gpio20", "gpio21";
344 pins = "gpio20", "gpio21";
345 drive-strength = <16>;
350 i2c_1_pins: i2c_1_pinmux {
352 function = "blsp_i2c1";
353 pins = "gpio34", "gpio35";
356 pins = "gpio34", "gpio35";
357 drive-strength = <16>;
362 nand_pins: nand_pins {
364 * There are 18 pins. 15 pins are common between LCD and NAND.
365 * The QPIC controller arbitrates between LCD and NAND. Of the
366 * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
368 * The meraki source hints that the bluetooth module claims
369 * pin 52 as well. But sadly, there's no data whenever this
370 * is a NAND or LCD exclusive pin or not.
374 pins = "gpio52", "gpio53", "gpio58",
381 pins = "gpio54", "gpio55", "gpio56",
382 "gpio57", "gpio60", "gpio61",
383 "gpio62", "gpio63", "gpio64",
384 "gpio65", "gpio66", "gpio67",
394 qcom,ath10k-calibration-variant = "Meraki-MR33";
399 qcom,ath10k-calibration-variant = "Meraki-MR33";