2 * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all copies.
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
13 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
28 #include <linux/vmalloc.h>
29 #include <linux/pagemap.h>
30 #include <linux/smp.h>
31 #include <linux/platform_device.h>
33 #include <linux/of_device.h>
34 #include <linux/clk.h>
35 #include <linux/kernel.h>
36 #include <linux/device.h>
37 #include <linux/sysctl.h>
38 #include <linux/phy.h>
39 #include <linux/of_net.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <asm-generic/bug.h>
45 #define EDMA_CPU_CORES_SUPPORTED 4
46 #define EDMA_MAX_PORTID_SUPPORTED 5
47 #define EDMA_MAX_VLAN_SUPPORTED EDMA_MAX_PORTID_SUPPORTED
48 #define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)
49 #define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f /* 0001_1111 = 0x1f */
50 #define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */
52 #define EDMA_MAX_RECEIVE_QUEUE 8
53 #define EDMA_MAX_TRANSMIT_QUEUE 16
55 /* WAN/LAN adapter number */
60 #define EDMA_LAN_DEFAULT_VLAN 1
61 #define EDMA_WAN_DEFAULT_VLAN 2
63 #define EDMA_DEFAULT_GROUP1_VLAN 1
64 #define EDMA_DEFAULT_GROUP2_VLAN 2
65 #define EDMA_DEFAULT_GROUP3_VLAN 3
66 #define EDMA_DEFAULT_GROUP4_VLAN 4
67 #define EDMA_DEFAULT_GROUP5_VLAN 5
69 /* Queues exposed to linux kernel */
70 #define EDMA_NETDEV_TX_QUEUE 4
71 #define EDMA_NETDEV_RX_QUEUE 4
73 /* Number of queues per core */
74 #define EDMA_NUM_TXQ_PER_CORE 4
75 #define EDMA_NUM_RXQ_PER_CORE 2
77 #define EDMA_TPD_EOP_SHIFT 31
79 #define EDMA_PORT_ID_SHIFT 12
80 #define EDMA_PORT_ID_MASK 0x7
82 /* tpd word 3 bit 18-28 */
83 #define EDMA_TPD_PORT_BITMAP_SHIFT 18
85 #define EDMA_TPD_FROM_CPU_SHIFT 25
87 #define EDMA_FROM_CPU_MASK 0x80
88 #define EDMA_SKB_PRIORITY_MASK 0x38
90 /* TX/RX descriptor ring count */
91 /* should be a power of 2 */
92 #define EDMA_RX_RING_SIZE 128
93 #define EDMA_TX_RING_SIZE 128
95 /* Flags used in paged/non paged mode */
96 #define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256
97 #define EDMA_RX_HEAD_BUFF_SIZE 1540
99 /* MAX frame size supported by switch */
100 #define EDMA_MAX_JUMBO_FRAME_SIZE 9216
103 #define EDMA_INTR_CLEAR_TYPE 0
104 #define EDMA_INTR_SW_IDX_W_TYPE 0
105 #define EDMA_FIFO_THRESH_TYPE 0
106 #define EDMA_RSS_TYPE 0
107 #define EDMA_RX_IMT 0x0020
108 #define EDMA_TX_IMT 0x0050
109 #define EDMA_TPD_BURST 5
110 #define EDMA_TXF_BURST 0x100
111 #define EDMA_RFD_BURST 8
112 #define EDMA_RFD_THR 16
113 #define EDMA_RFD_LTHR 0
115 /* RX/TX per CPU based mask/shift */
116 #define EDMA_TX_PER_CPU_MASK 0xF
117 #define EDMA_RX_PER_CPU_MASK 0x3
118 #define EDMA_TX_PER_CPU_MASK_SHIFT 0x2
119 #define EDMA_RX_PER_CPU_MASK_SHIFT 0x1
120 #define EDMA_TX_CPU_START_SHIFT 0x2
121 #define EDMA_RX_CPU_START_SHIFT 0x1
123 /* FLags used in transmit direction */
124 #define EDMA_HW_CHECKSUM 0x00000001
125 #define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002
126 #define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004
128 #define EDMA_SW_DESC_FLAG_LAST 0x1
129 #define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2
130 #define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4
131 #define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8
132 #define EDMA_SW_DESC_FLAG_SKB_NONE 0x10
133 #define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20
136 #define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)
138 /* Ethtool specific list of EDMA supported features */
139 #define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \
140 | SUPPORTED_10baseT_Full \
141 | SUPPORTED_100baseT_Half \
142 | SUPPORTED_100baseT_Full \
143 | SUPPORTED_1000baseT_Full)
145 /* Recevie side atheros Header */
146 #define EDMA_RX_ATH_HDR_VERSION 0x2
147 #define EDMA_RX_ATH_HDR_VERSION_SHIFT 14
148 #define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11
149 #define EDMA_RX_ATH_PORT_TYPE_SHIFT 6
150 #define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4
152 /* Transmit side atheros Header */
153 #define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F
154 #define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80
155 #define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7
157 #define EDMA_TXQ_START_CORE0 8
158 #define EDMA_TXQ_START_CORE1 12
159 #define EDMA_TXQ_START_CORE2 0
160 #define EDMA_TXQ_START_CORE3 4
162 #define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00
163 #define EDMA_TXQ_IRQ_MASK_CORE1 0xF000
164 #define EDMA_TXQ_IRQ_MASK_CORE2 0x000F
165 #define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0
167 #define EDMA_ETH_HDR_LEN 12
168 #define EDMA_ETH_TYPE_MASK 0xFFFF
170 #define EDMA_RX_BUFFER_WRITE 16
171 #define EDMA_RFD_AVAIL_THR 80
173 #define EDMA_GMAC_NO_MDIO_PHY PHY_MAX_ADDR
175 extern int ssdk_rfs_ipct_rule_set(__be32 ip_src
, __be32 ip_dst
,
176 __be16 sport
, __be16 dport
,
177 uint8_t proto
, u16 loadbalance
, bool action
);
178 struct edma_ethtool_statistics
{
228 u32 rx_alloc_fail_ctr
;
231 struct edma_mdio_data
{
232 struct mii_bus
*mii_bus
;
233 void __iomem
*membase
;
234 int phy_irq
[PHY_MAX_ADDR
];
237 /* EDMA LINK state */
238 enum edma_link_state
{
239 __EDMA_LINKUP
, /* Indicate link is UP */
240 __EDMA_LINKDOWN
/* Indicate link is down */
243 /* EDMA GMAC state */
244 enum edma_gmac_state
{
245 __EDMA_UP
/* use to indicate GMAC is up */
248 /* edma transmit descriptor */
249 struct edma_tx_desc
{
250 __le16 len
; /* full packet including CRC */
251 __le16 svlan_tag
; /* vlan tag */
252 __le32 word1
; /* byte 4-7 */
253 __le32 addr
; /* address of buffer */
254 __le32 word3
; /* byte 12 */
257 /* edma receive return descriptor */
258 struct edma_rx_return_desc
{
270 struct edma_rx_free_desc
{
271 __le32 buffer_addr
; /* buffer address */
274 /* edma hw specific data */
276 u32 __iomem
*hw_addr
; /* inner register address */
277 struct edma_adapter
*adapter
; /* netdevice adapter */
278 u32 rx_intr_mask
; /*rx interrupt mask */
279 u32 tx_intr_mask
; /* tx interrupt nask */
280 u32 misc_intr_mask
; /* misc interrupt mask */
281 u32 wol_intr_mask
; /* wake on lan interrupt mask */
282 bool intr_clear_type
; /* interrupt clear */
283 bool intr_sw_idx_w
; /* interrupt software index */
284 u32 rx_head_buff_size
; /* Rx buffer size */
285 u8 rss_type
; /* rss protocol type */
288 /* edma_sw_desc stores software descriptor
289 * SW descriptor has 1:1 map with HW descriptor
291 struct edma_sw_desc
{
293 dma_addr_t dma
; /* dma address */
294 u16 length
; /* Tx/Rx buffer length */
298 /* per core related information */
299 struct edma_per_cpu_queues_info
{
300 struct napi_struct napi
; /* napi associated with the core */
301 u32 tx_mask
; /* tx interrupt mask */
302 u32 rx_mask
; /* rx interrupt mask */
303 u32 tx_status
; /* tx interrupt status */
304 u32 rx_status
; /* rx interrupt status */
305 u32 tx_start
; /* tx queue start */
306 u32 rx_start
; /* rx queue start */
307 struct edma_common_info
*edma_cinfo
; /* edma common info */
310 /* edma specific common info */
311 struct edma_common_info
{
312 struct edma_tx_desc_ring
*tpd_ring
[16]; /* 16 Tx queues */
313 struct edma_rfd_desc_ring
*rfd_ring
[8]; /* 8 Rx queues */
314 struct platform_device
*pdev
; /* device structure */
315 struct net_device
*netdev
[EDMA_MAX_PORTID_SUPPORTED
];
316 struct net_device
*portid_netdev_lookup_tbl
[EDMA_MAX_PORTID_BITMAP_INDEX
];
317 struct ctl_table_header
*edma_ctl_table_hdr
;
319 struct edma_ethtool_statistics edma_ethstats
; /* ethtool stats */
320 int num_rx_queues
; /* number of rx queue */
321 u32 num_tx_queues
; /* number of tx queue */
322 u32 tx_irq
[16]; /* number of tx irq */
323 u32 rx_irq
[8]; /* number of rx irq */
324 u32 from_cpu
; /* from CPU TPD field */
325 u32 num_rxq_per_core
; /* Rx queues per core */
326 u32 num_txq_per_core
; /* Tx queues per core */
327 u16 tx_ring_count
; /* Tx ring count */
328 u16 rx_ring_count
; /* Rx ring*/
329 u16 rx_head_buffer_len
; /* rx buffer length */
330 u16 rx_page_buffer_len
; /* rx buffer length */
331 u32 page_mode
; /* Jumbo frame supported flag */
332 u32 fraglist_mode
; /* fraglist supported flag */
333 struct edma_hw hw
; /* edma hw specific structure */
334 struct edma_per_cpu_queues_info edma_percpu_info
[CONFIG_NR_CPUS
]; /* per cpu information */
335 spinlock_t stats_lock
; /* protect edma stats area for updation */
336 struct timer_list edma_stats_timer
;
338 void __iomem
*ess_hw_addr
;
342 /* transimit packet descriptor (tpd) ring */
343 struct edma_tx_desc_ring
{
344 struct netdev_queue
*nq
[EDMA_MAX_NETDEV_PER_QUEUE
]; /* Linux queue index */
345 struct net_device
*netdev
[EDMA_MAX_NETDEV_PER_QUEUE
];
346 /* Array of netdevs associated with the tpd ring */
347 void *hw_desc
; /* descriptor ring virtual address */
348 struct edma_sw_desc
*sw_desc
; /* buffer associated with ring */
349 int netdev_bmp
; /* Bitmap for per-ring netdevs */
350 u32 size
; /* descriptor ring length in bytes */
351 u16 count
; /* number of descriptors in the ring */
352 dma_addr_t dma
; /* descriptor ring physical address */
353 u16 sw_next_to_fill
; /* next Tx descriptor to fill */
354 u16 sw_next_to_clean
; /* next Tx descriptor to clean */
357 /* receive free descriptor (rfd) ring */
358 struct edma_rfd_desc_ring
{
359 void *hw_desc
; /* descriptor ring virtual address */
360 struct edma_sw_desc
*sw_desc
; /* buffer associated with ring */
361 u16 size
; /* bytes allocated to sw_desc */
362 u16 count
; /* number of descriptors in the ring */
363 dma_addr_t dma
; /* descriptor ring physical address */
364 u16 sw_next_to_fill
; /* next descriptor to fill */
365 u16 sw_next_to_clean
; /* next descriptor to clean */
366 u16 pending_fill
; /* fill pending from previous iteration */
369 /* edma_rfs_flter_node - rfs filter node in hash table */
370 struct edma_rfs_filter_node
{
371 struct flow_keys keys
;
372 u32 flow_id
; /* flow_id of filter provided by kernel */
373 u16 filter_id
; /* filter id of filter returned by adaptor */
374 u16 rq_id
; /* desired rq index */
375 struct hlist_node node
; /* edma rfs list node */
378 /* edma_rfs_flow_tbl - rfs flow table */
379 struct edma_rfs_flow_table
{
380 u16 max_num_filter
; /* Maximum number of filters edma supports */
381 u16 hashtoclean
; /* hash table index to clean next */
382 int filter_available
; /* Number of free filters available */
383 struct hlist_head hlist_head
[EDMA_RFS_FLOW_ENTRIES
];
384 spinlock_t rfs_ftab_lock
;
385 struct timer_list expire_rfs
; /* timer function for edma_rps_may_expire_flow */
388 /* EDMA net device structure */
389 struct edma_adapter
{
390 struct net_device
*netdev
; /* netdevice */
391 struct platform_device
*pdev
; /* platform device */
392 struct edma_common_info
*edma_cinfo
; /* edma common info */
393 struct phy_device
*phydev
; /* Phy device */
394 struct edma_rfs_flow_table rfs
; /* edma rfs flow table */
395 struct net_device_stats stats
; /* netdev statistics */
396 set_rfs_filter_callback_t set_rfs_rule
;
397 u32 flags
;/* status flags */
398 unsigned long state_flags
; /* GMAC up/down flags */
399 u32 forced_speed
; /* link force speed */
400 u32 forced_duplex
; /* link force duplex */
401 u32 link_state
; /* phy link state */
402 u32 phy_mdio_addr
; /* PHY device address on MII interface */
403 u32 poll_required
; /* check if link polling is required */
404 u32 tx_start_offset
[CONFIG_NR_CPUS
]; /* tx queue start */
405 u32 default_vlan_tag
; /* vlan tag */
407 uint8_t phy_id
[MII_BUS_ID_SIZE
+ 3];
410 int edma_alloc_queues_tx(struct edma_common_info
*edma_cinfo
);
411 int edma_alloc_queues_rx(struct edma_common_info
*edma_cinfo
);
412 int edma_open(struct net_device
*netdev
);
413 int edma_close(struct net_device
*netdev
);
414 void edma_free_tx_resources(struct edma_common_info
*edma_c_info
);
415 void edma_free_rx_resources(struct edma_common_info
*edma_c_info
);
416 int edma_alloc_tx_rings(struct edma_common_info
*edma_cinfo
);
417 int edma_alloc_rx_rings(struct edma_common_info
*edma_cinfo
);
418 void edma_free_tx_rings(struct edma_common_info
*edma_cinfo
);
419 void edma_free_rx_rings(struct edma_common_info
*edma_cinfo
);
420 void edma_free_queues(struct edma_common_info
*edma_cinfo
);
421 void edma_irq_disable(struct edma_common_info
*edma_cinfo
);
422 int edma_reset(struct edma_common_info
*edma_cinfo
);
423 int edma_poll(struct napi_struct
*napi
, int budget
);
424 netdev_tx_t
edma_xmit(struct sk_buff
*skb
,
425 struct net_device
*netdev
);
426 int edma_configure(struct edma_common_info
*edma_cinfo
);
427 void edma_irq_enable(struct edma_common_info
*edma_cinfo
);
428 void edma_enable_tx_ctrl(struct edma_hw
*hw
);
429 void edma_enable_rx_ctrl(struct edma_hw
*hw
);
430 void edma_stop_rx_tx(struct edma_hw
*hw
);
431 void edma_free_irqs(struct edma_adapter
*adapter
);
432 irqreturn_t
edma_interrupt(int irq
, void *dev
);
433 void edma_write_reg(u16 reg_addr
, u32 reg_value
);
434 void edma_read_reg(u16 reg_addr
, volatile u32
*reg_value
);
435 struct net_device_stats
*edma_get_stats(struct net_device
*netdev
);
436 int edma_set_mac_addr(struct net_device
*netdev
, void *p
);
437 int edma_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
438 u16 rxq
, u32 flow_id
);
439 int edma_register_rfs_filter(struct net_device
*netdev
,
440 set_rfs_filter_callback_t set_filter
);
441 void edma_flow_may_expire(struct timer_list
*t
);
442 void edma_set_ethtool_ops(struct net_device
*netdev
);
443 void edma_set_stp_rstp(bool tag
);
444 void edma_assign_ath_hdr_type(int tag
);
445 int edma_get_default_vlan_tag(struct net_device
*netdev
);
446 void edma_adjust_link(struct net_device
*netdev
);
447 int edma_fill_netdev(struct edma_common_info
*edma_cinfo
, int qid
, int num
, int txq_id
);
448 void edma_read_append_stats(struct edma_common_info
*edma_cinfo
);
449 void edma_change_tx_coalesce(int usecs
);
450 void edma_change_rx_coalesce(int usecs
);
451 void edma_get_tx_rx_coalesce(u32
*reg_val
);
452 void edma_clear_irq_status(void);
453 void ess_set_port_status_speed(struct edma_common_info
*edma_cinfo
,
454 struct phy_device
*phydev
, uint8_t port_id
);
455 #endif /* _EDMA_H_ */