1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/soc/qcom,tcsr.h>
22 pinctrl-0 = <&mdio_pins>;
23 pinctrl-names = "default";
27 compatible = "qcom,qca-gcnt";
32 compatible = "qcom,tcsr";
33 reg = <0x1949000 0x100>;
34 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
40 compatible = "qcom,tcsr";
41 reg = <0x194b000 0x100>;
42 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
46 compatible = "qcom,tcsr";
47 reg = <0x1953000 0x1000>;
48 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
52 compatible = "qcom,tcsr";
53 reg = <0x1957000 0x100>;
54 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
76 mdio_pins: mdio_pinmux {
88 pins = "gpio52", "gpio53";
93 serial_pins: serial_pinmux {
95 pins = "gpio60", "gpio61";
96 function = "blsp_uart0";
101 spi_0_pins: spi_0_pinmux {
103 function = "blsp_spi0";
104 pins = "gpio55", "gpio56", "gpio57";
105 drive-strength = <2>;
111 pins = "gpio54", "gpio59";
112 drive-strength = <2>;
126 pinctrl-0 = <&spi_0_pins>;
127 pinctrl-names = "default";
128 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
133 compatible = "jedec,spi-nor";
135 spi-max-frequency = <24000000>;
138 compatible = "fixed-partitions";
139 #address-cells = <1>;
144 reg = <0x00000000 0x00040000>;
150 reg = <0x00040000 0x00020000>;
156 reg = <0x00060000 0x00060000>;
162 reg = <0x000c0000 0x00010000>;
168 reg = <0x000d0000 0x00010000>;
173 label = "APPSBLENV"; /* uboot env*/
174 reg = <0x000e0000 0x00010000>;
179 label = "APPSBL"; /* uboot */
180 reg = <0x000f0000 0x00080000>;
186 reg = <0x00170000 0x00010000>;
190 compatible = "fixed-layout";
191 #address-cells = <1>;
194 precal_art_1000: precal@1000 {
195 reg = <0x1000 0x2f20>;
198 precal_art_5000: precal@5000 {
199 reg = <0x5000 0x2f20>;
209 compatible = "spi-nand";
211 spi-max-frequency = <24000000>;
214 compatible = "fixed-partitions";
215 #address-cells = <1>;
220 reg = <0x00000000 0x08000000>;
229 pinctrl-0 = <&serial_pins>;
230 pinctrl-names = "default";
257 nvmem-cell-names = "pre-calibration";
258 nvmem-cells = <&precal_art_1000>;
259 qcom,ath10k-calibration-variant = "8devices-Jalapeno";
264 nvmem-cell-names = "pre-calibration";
265 nvmem-cells = <&precal_art_5000>;
266 qcom,ath10k-calibration-variant = "8devices-Jalapeno";