target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-ecw5211.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/leds/common.h>
   7 #include <dt-bindings/soc/qcom,tcsr.h>
   8
   9 / {
  10         model = "Edgecore ECW5211";
  11         compatible = "edgecore,ecw5211";
  12
  13         aliases {
  14                 led-boot = &led_power;
  15                 led-failsafe = &led_power;
  16                 led-running = &led_power;
  17                 led-upgrade = &led_power;
  18                 ethernet0 = &swport5;
  19                 ethernet1 = &gmac;
  20         };
  21
  22         chosen {
  23                 bootargs-append = " root=/dev/ubiblock0_1";
  24         };
  25
  26         keys {
  27                 compatible = "gpio-keys";
  28
  29                 reset {
  30                         label = "reset";
  31                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  32                         linux,code = <KEY_RESTART>;
  33                 };
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38
  39                 led_power: power {
  40                         function = LED_FUNCTION_POWER;
  41                         color = <LED_COLOR_ID_YELLOW>;
  42                         gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
  43                 };
  44
  45                 wlan2g {
  46                         label = "green:wlan2g";
  47                         gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
  48                         linux,default-trigger = "phy0tpt";
  49                 };
  50
  51                 wlan5g {
  52                         label = "green:wlan5g";
  53                         gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
  54                         linux,default-trigger = "phy1tpt";
  55                 };
  56         };
  57
  58         soc {
  59                 counter@4a1000 {
  60                         compatible = "qcom,qca-gcnt";
  61                         reg = <0x4a1000 0x4>;
  62                 };
  63
  64                 tcsr@1949000 {
  65                         compatible = "qcom,tcsr";
  66                         reg = <0x1949000 0x100>;
  67                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  68                 };
  69
  70                 tcsr@194b000 {
  71                         compatible = "qcom,tcsr";
  72                         reg = <0x194b000 0x100>;
  73                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  74                 };
  75
  76                 ess_tcsr@1953000 {
  77                         compatible = "qcom,tcsr";
  78                         reg = <0x1953000 0x1000>;
  79                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  80                 };
  81
  82                 tcsr@1957000 {
  83                         compatible = "qcom,tcsr";
  84                         reg = <0x1957000 0x100>;
  85                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  86                 };
  87
  88                 crypto@8e3a000 {
  89                         status = "okay";
  90                 };
  91         };
  92 };
  93
  94 &watchdog {
  95         status = "okay";
  96 };
  97
  98 &prng {
  99         status = "okay";
 100 };
 101
 102 &tlmm {
 103         mdio_pins: mdio_pinmux {
 104                 mux_mdio {
 105                         pins = "gpio53";
 106                         function = "mdio";
 107                         bias-pull-up;
 108                 };
 109
 110                 mux_mdc {
 111                         pins = "gpio52";
 112                         function = "mdc";
 113                         bias-pull-up;
 114                 };
 115         };
 116
 117         serial_pins: serial_pinmux {
 118                 mux {
 119                         pins = "gpio60", "gpio61";
 120                         function = "blsp_uart0";
 121                         bias-disable;
 122                 };
 123         };
 124
 125         spi0_pins: spi0_pinmux {
 126                 pin {
 127                         function = "blsp_spi0";
 128                         pins = "gpio55", "gpio56", "gpio57";
 129                         drive-strength = <2>;
 130                         bias-disable;
 131                 };
 132
 133                 pin_cs {
 134                         function = "gpio";
 135                         pins = "gpio54", "gpio4";
 136                         drive-strength = <2>;
 137                         bias-disable;
 138                         output-high;
 139                 };
 140         };
 141
 142         i2c0_pins: i2c0_pinmux {
 143                 mux_i2c {
 144                         function = "blsp_i2c0";
 145                         pins = "gpio58", "gpio59";
 146                         drive-strength = <16>;
 147                         bias-disable;
 148                 };
 149         };
 150 };
 151
 152 &blsp_dma {
 153         status = "okay";
 154 };
 155
 156 &blsp1_spi1 {
 157         status = "okay";
 158
 159         pinctrl-0 = <&spi0_pins>;
 160         pinctrl-names = "default";
 161         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
 162
 163         flash@0 {
 164                 compatible = "jedec,spi-nor";
 165                 reg = <0>;
 166                 spi-max-frequency = <24000000>;
 167
 168                 partitions {
 169                         compatible = "fixed-partitions";
 170                         #address-cells = <1>;
 171                         #size-cells = <1>;
 172
 173                         partition@0 {
 174                                 label = "0:SBL1";
 175                                 reg = <0x00000000 0x00040000>;
 176                                 read-only;
 177                         };
 178
 179                         partition@40000 {
 180                                 label = "0:MIBIB";
 181                                 reg = <0x00040000 0x00020000>;
 182                                 read-only;
 183                         };
 184
 185                         partition@60000 {
 186                                 label = "0:QSEE";
 187                                 reg = <0x00060000 0x00060000>;
 188                                 read-only;
 189                         };
 190
 191                         partition@c0000 {
 192                                 label = "0:CDT";
 193                                 reg = <0x000c0000 0x00010000>;
 194                                 read-only;
 195                         };
 196
 197                         partition@d0000 {
 198                                 label = "0:DDRPARAMS";
 199                                 reg = <0x000d0000 0x00010000>;
 200                                 read-only;
 201                         };
 202
 203                         partition@e0000 {
 204                                 label = "0:APPSBLENV"; /* uboot env */
 205                                 reg = <0x000e0000 0x00010000>;
 206                         };
 207
 208                         partition@f0000 {
 209                                 label = "0:APPSBL"; /* uboot */
 210                                 reg = <0x000f0000 0x00080000>;
 211                                 read-only;
 212                         };
 213
 214                         partition@170000 {
 215                                 label = "0:ART";
 216                                 reg = <0x00170000 0x00010000>;
 217                                 read-only;
 218
 219                                 nvmem-layout {
 220                                         compatible = "fixed-layout";
 221                                         #address-cells = <1>;
 222                                         #size-cells = <1>;
 223
 224                                         precal_art_1000: precal@1000 {
 225                                                 reg = <0x1000 0x2f20>;
 226                                         };
 227
 228                                         precal_art_5000: precal@5000 {
 229                                                 reg = <0x5000 0x2f20>;
 230                                         };
 231                                 };
 232                         };
 233                 };
 234         };
 235
 236         flash@1 {
 237                 compatible = "spi-nand";
 238                 reg = <1>;
 239                 spi-max-frequency = <24000000>;
 240
 241                 partitions {
 242                         compatible = "fixed-partitions";
 243                         #address-cells = <1>;
 244                         #size-cells = <1>;
 245
 246                         partition@0 {
 247                                 label = "rootfs";
 248                                 reg = <0x00000000 0x04000000>;
 249                         };
 250                 };
 251         };
 252 };
 253
 254 &blsp1_i2c3 {
 255         status = "okay";
 256
 257         pinctrl-0 = <&i2c0_pins>;
 258         pinctrl-names = "default";
 259
 260         tpm@29 {
 261                 compatible = "atmel,at97sc3204t";
 262                 reg = <0x29>;
 263         };
 264 };
 265
 266 &blsp1_uart1 {
 267         status = "okay";
 268
 269         pinctrl-0 = <&serial_pins>;
 270         pinctrl-names = "default";
 271 };
 272
 273 &cryptobam {
 274         status = "okay";
 275 };
 276
 277 &mdio {
 278         status = "okay";
 279
 280         pinctrl-0 = <&mdio_pins>;
 281         pinctrl-names = "default";
 282 };
 283
 284 &gmac {
 285         status = "okay";
 286 };
 287
 288 &switch {
 289         status = "okay";
 290 };
 291
 292 &swport4 {
 293         status = "okay";
 294
 295         label = "lan";
 296 };
 297
 298 &swport5 {
 299         status = "okay";
 300 };
 301
 302 &wifi0 {
 303         status = "okay";
 304         nvmem-cell-names = "pre-calibration";
 305         nvmem-cells = <&precal_art_1000>;
 306 };
 307
 308 &wifi1 {
 309         status = "okay";
 310         nvmem-cell-names = "pre-calibration";
 311         nvmem-cells = <&precal_art_5000>;
 312         qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
 313 };
 314
 315 &usb2_hs_phy {
 316         status = "okay";
 317 };
 318
 319 &usb2 {
 320         status = "okay";
 321 };
 322
 323 &usb3_hs_phy {
 324         status = "okay";
 325 };
 326
 327 &usb3 {
 328         status = "okay";
 329 };
 330
 331 &usb3_dwc {
 332         phys = <&usb3_hs_phy>;
 333         phy-names = "usb2-phy";
 334 };