target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-ap-303h.dts

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "Aruba AP-303H";
  10         compatible = "aruba,ap-303h";
  11
  12         aliases {
  13                 led-boot = &led_system_green;
  14                 led-failsafe = &led_system_red;
  15                 led-running = &led_system_green;
  16                 led-upgrade = &led_system_amber;
  17         };
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x10000000>;
  22         };
  23
  24         soc {
  25                 counter@4a1000 {
  26                         compatible = "qcom,qca-gcnt";
  27                         reg = <0x4a1000 0x4>;
  28                 };
  29
  30                 ess_tcsr@1953000 {
  31                         compatible = "qcom,tcsr";
  32                         reg = <0x1953000 0x1000>;
  33                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  34                 };
  35
  36                 tcsr@1949000 {
  37                         compatible = "qcom,tcsr";
  38                         reg = <0x1949000 0x100>;
  39                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  40                 };
  41
  42                 tcsr@194b000 {
  43                         compatible = "qcom,tcsr";
  44                         reg = <0x194b000 0x100>;
  45                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  46                 };
  47
  48                 tcsr@1957000 {
  49                         compatible = "qcom,tcsr";
  50                         reg = <0x1957000 0x100>;
  51                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  52                 };
  53         };
  54
  55         leds {
  56                 compatible = "gpio-leds";
  57
  58                 wifi_green {
  59                         label = "green:wifi";
  60                         gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
  61                         linux,default-trigger = "phy0tpt";
  62                 };
  63
  64                 wifi_amber {
  65                         label = "amber:wifi";
  66                         gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
  67                         linux,default-trigger = "phy1tpt";
  68                 };
  69
  70                 pse {
  71                         label = "green:pse";
  72                         gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
  73                 };
  74
  75                 led_system_red: system_red {
  76                         label = "red:system";
  77                         gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
  78                 };
  79
  80                 led_system_green: system_green {
  81                         label = "green:system";
  82                         gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
  83                 };
  84
  85                 led_system_amber: system_amber {
  86                         label = "amber:system";
  87                         gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
  88                 };
  89         };
  90
  91         keys {
  92                 compatible = "gpio-keys";
  93
  94                 reset {
  95                         label = "Reset button";
  96                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  97                         linux,code = <KEY_RESTART>;
  98                 };
  99         };
 100 };
 101
 102 &watchdog {
 103         status = "okay";
 104 };
 105
 106 &prng {
 107         status = "okay";
 108 };
 109
 110 &crypto {
 111         status = "okay";
 112 };
 113
 114 &blsp_dma {
 115         status = "okay";
 116 };
 117
 118 &blsp1_uart1 {
 119         pinctrl-0 = <&serial_0_pins>;
 120         pinctrl-names = "default";
 121         status = "okay";
 122 };
 123
 124 &blsp1_uart2 {
 125         /* Texas Instruments CC2540T BLE radio */
 126         pinctrl-0 = <&serial_1_pins>;
 127         pinctrl-names = "default";
 128         status = "okay";
 129 };
 130
 131 &cryptobam {
 132         status = "okay";
 133 };
 134
 135 &qpic_bam {
 136         status = "okay";
 137 };
 138
 139 &tlmm {
 140         /*
 141          * In addition to the Pins listed below,
 142          * the following GPIOs have "features":
 143          * 39 - out - active low to force HW reset
 144          * 32 - out - active low to reset TPM
 145          * 43 - out - active low to reset BLE radio
 146          * 41 - out - pulse to set warm reset status
 147          * 34 - out - active low to enable PSE port
 148          * 22 - in  - active low when 802.3at powered
 149          * 29 - in  - active high when DC powered
 150          * 40 - in  - active low when reset due to cold HW reset
 151          * 30 - in  - active low when USB overcurrent detected
 152          * 35 - in  - interrupt line for power monitor chip
 153          * 31 - in  - active low when PSE port active
 154          */
 155         mdio_pins: mdio_pinmux {
 156                 mux_1 {
 157                         pins = "gpio6";
 158                         function = "mdio";
 159                         bias-pull-up;
 160                 };
 161                 mux_2 {
 162                         pins = "gpio7";
 163                         function = "mdc";
 164                         bias-pull-up;
 165                 };
 166         };
 167
 168         spi_0_pins: spi_0_pinmux {
 169                 pin {
 170                         function = "blsp_spi0";
 171                         pins = "gpio13", "gpio14", "gpio15";
 172                         drive-strength = <12>;
 173                         bias-disable;
 174                 };
 175                 pin_cs {
 176                         function = "gpio";
 177                         pins = "gpio12", "gpio59";
 178                         drive-strength = <2>;
 179                         bias-disable;
 180                         output-high;
 181                 };
 182         };
 183
 184         i2c_0_pins: i2c_0_pinmux {
 185                 mux {
 186                         pins = "gpio20", "gpio21";
 187                         function = "blsp_i2c0";
 188                         drive-strength = <4>;
 189                         bias-pull-up;
 190                 };
 191         };
 192
 193         serial_0_pins: serial_0_pinmux {
 194                 mux {
 195                         pins = "gpio16", "gpio17";
 196                         function = "blsp_uart0";
 197                         bias-disable;
 198                 };
 199         };
 200
 201         serial_1_pins: serial_1_pinmux {
 202                 mux {
 203                         pins = "gpio8", "gpio9";
 204                         function = "blsp_uart1";
 205                         bias-disable;
 206                 };
 207         };
 208
 209         usb-power {
 210                 line-name = "USB-power";
 211                 gpios = <23 GPIO_ACTIVE_HIGH>;
 212                 gpio-hog;
 213                 output-high;
 214         };
 215 };
 216
 217 &blsp1_i2c3 {
 218         pinctrl-0 = <&i2c_0_pins>;
 219         pinctrl-names = "default";
 220         status = "okay";
 221         clock-frequency = <400000>;
 222
 223         tpm@29 {
 224                 /* No Driver */
 225                 compatible = "atmel,at97sc3203";
 226                 reg = <0x29>;
 227                 read-only;
 228         };
 229
 230         power-monitor@40 {
 231                 /* No driver */
 232                 /* Device also replies on address 0x3f, see   */
 233                 /* ISL28022 datasheet, "Broadcast Addressing" */
 234                 compatible = "isl,isl28022";
 235                 reg = <0x40>;
 236         };
 237 };
 238
 239 &blsp1_spi1 {
 240         pinctrl-0 = <&spi_0_pins>;
 241         pinctrl-names = "default";
 242         status = "okay";
 243         cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
 244
 245         flash@0 {
 246                 compatible = "jedec,spi-nor";
 247                 reg = <0>;
 248                 spi-max-frequency = <24000000>;
 249
 250                 partitions {
 251                         compatible = "fixed-partitions";
 252                         #address-cells = <1>;
 253                         #size-cells = <1>;
 254
 255                         /*
 256                          * There is no partition map for the NOR flash
 257                          * in the stock firmware.
 258                          *
 259                          * All partitions here are based on offsets
 260                          * found in the U-Boot GPL code and information
 261                          * from smem.
 262                          */
 263
 264                         partition@0 {
 265                                 label = "sbl1";
 266                                 reg = <0x0 0x40000>;
 267                                 read-only;
 268                         };
 269
 270                         partition@40000 {
 271                                 label = "mibib";
 272                                 reg = <0x40000 0x20000>;
 273                                 read-only;
 274                         };
 275
 276                         partition@60000 {
 277                                 label = "qsee";
 278                                 reg = <0x60000 0x60000>;
 279                                 read-only;
 280                         };
 281
 282                         partition@c0000 {
 283                                 label = "cdt";
 284                                 reg = <0xc0000 0x10000>;
 285                                 read-only;
 286                         };
 287
 288                         partition@d0000 {
 289                                 label = "ddrparams";
 290                                 reg = <0xd0000 0x10000>;
 291                                 read-only;
 292                         };
 293
 294                         partition@e0000 {
 295                                 label = "appsblenv";
 296                                 reg = <0xe0000 0x10000>;
 297                                 read-only;
 298                         };
 299
 300                         partition@f0000 {
 301                                 label = "appsbl";
 302                                 reg = <0xf0000 0x100000>;
 303                                 read-only;
 304                         };
 305
 306                         partition@1e0000 {
 307                                 label = "ART";
 308                                 reg = <0x1f0000 0x10000>;
 309                                 read-only;
 310
 311                                 nvmem-layout {
 312                                         compatible = "fixed-layout";
 313                                         #address-cells = <1>;
 314                                         #size-cells = <1>;
 315
 316                                         precal_art_1000: precal@1000 {
 317                                                 reg = <0x1000 0x2f20>;
 318                                         };
 319
 320                                         precal_art_5000: precal@5000 {
 321                                                 reg = <0x5000 0x2f20>;
 322                                         };
 323                                 };
 324                         };
 325
 326                         partition@1f0000 {
 327                                 label = "osss";
 328                                 reg = <0x200000 0x170000>;
 329                                 read-only;
 330                         };
 331
 332                         partition@200000 {
 333                                 label = "pds";
 334                                 reg = <0x370000 0x10000>;
 335                                 read-only;
 336                         };
 337
 338                         partition@380000 {
 339                                 label = "apcd";
 340                                 reg = <0x380000 0x10000>;
 341                                 read-only;
 342                         };
 343
 344                         partition@390000 {
 345                                 label = "mfginfo";
 346                                 reg = <0x390000 0x10000>;
 347                                 read-only;
 348
 349                                 nvmem-layout {
 350                                         compatible = "fixed-layout";
 351                                         #address-cells = <1>;
 352                                         #size-cells = <1>;
 353
 354                                         macaddr_mfginfo_1d: macaddr@1d {
 355                                                 compatible = "mac-base";
 356                                                 reg = <0x1d 0x6>;
 357                                                 #nvmem-cell-cells = <1>;
 358                                         };
 359
 360                                         macaddr_mfginfo_45: macaddr@45 {
 361                                                 compatible = "mac-base";
 362                                                 reg = <0x45 0x6>;
 363                                                 #nvmem-cell-cells = <1>;
 364                                         };
 365                                 };
 366                         };
 367
 368                         partition@3a0000 {
 369                                 label = "fcache";
 370                                 reg = <0x3a0000 0x10000>;
 371                                 read-only;
 372                         };
 373
 374                         partition@3b0000 {
 375                                 /* Called osss1 in smem */
 376                                 label = "u-boot-env-bak";
 377                                 reg = <0x3b0000 0x10000>;
 378                                 read-only;
 379                         };
 380
 381                         partition@3f0000 {
 382                                 label = "u-boot-env";
 383                                 reg = <0x3c0000 0x40000>;
 384                                 read-only;
 385                         };
 386                 };
 387         };
 388
 389         flash@1 {
 390                 status = "okay";
 391
 392                 compatible = "spi-nand";
 393                 reg = <1>;
 394                 spi-max-frequency = <24000000>;
 395
 396                 partitions {
 397                         compatible = "fixed-partitions";
 398                         #address-cells = <1>;
 399                         #size-cells = <1>;
 400
 401                         partition@0 {
 402                                 /* 'aos0' in Aruba firmware */
 403                                 label = "aos0";
 404                                 reg = <0x0 0x2000000>;
 405                                 read-only;
 406                         };
 407
 408                         partition@2000000 {
 409                                 /* 'aos1' in Aruba firmware */
 410                                 label = "ubi";
 411                                 reg = <0x2000000 0x2000000>;
 412                         };
 413
 414                         partition@4000000 {
 415                                 label = "aruba-ubifs";
 416                                 reg = <0x4000000 0x4000000>;
 417                                 read-only;
 418                         };
 419                 };
 420         };
 421 };
 422
 423 &usb3 {
 424         status = "okay";
 425 };
 426
 427 &usb3_dwc {
 428         phys = <&usb3_hs_phy>;
 429         phy-names = "usb2-phy";
 430 };
 431
 432 &usb3_hs_phy {
 433         status = "okay";
 434 };
 435
 436 &mdio {
 437         status = "okay";
 438         pinctrl-0 = <&mdio_pins>;
 439         pinctrl-names = "default";
 440
 441         reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
 442         reset-delay-us = <2000>;
 443 };
 444
 445 &gmac {
 446         status = "okay";
 447
 448         nvmem-cell-names = "mac-address";
 449         nvmem-cells = <&macaddr_mfginfo_1d 1>;
 450 };
 451
 452 &switch {
 453         status = "okay";
 454 };
 455
 456 &swport2 {
 457         status = "okay";
 458
 459         label = "lan1";
 460 };
 461
 462 &swport3 {
 463         status = "okay";
 464
 465         label = "lan2";
 466 };
 467
 468 &swport4 {
 469         status = "okay";
 470
 471         label = "lan3";
 472 };
 473
 474 &swport5 {
 475         status = "okay";
 476
 477         label = "wan";
 478         nvmem-cell-names = "mac-address";
 479         nvmem-cells = <&macaddr_mfginfo_1d 0>;
 480 };
 481
 482 &wifi0 {
 483         status = "okay";
 484         nvmem-cell-names = "pre-calibration", "mac-address";
 485         nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_45 0>;
 486         qcom,ath10k-calibration-variant = "Aruba-AP-303";
 487 };
 488
 489 &wifi1 {
 490         status = "okay";
 491         nvmem-cell-names = "pre-calibration", "mac-address";
 492         nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_45 1>;
 493         qcom,ath10k-calibration-variant = "Aruba-AP-303";
 494 };