ipq40xx: use existing labels for prng node
[openwrt/staging/blogic.git] / target / linux / ipq40xx / files-6.6 / arch / arm / boot / dts / qcom / qcom-ipq4029-gl-s1300.dts
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/soc/qcom,tcsr.h>
8
9 / {
10 model = "GL.iNet GL-S1300";
11 compatible = "glinet,gl-s1300";
12
13 aliases {
14 led-boot = &led_power;
15 led-failsafe = &led_power;
16 led-running = &led_power;
17 led-upgrade = &led_power;
18 };
19
20 memory {
21 device_type = "memory";
22 reg = <0x80000000 0x10000000>;
23 };
24
25 soc {
26 mdio@90000 {
27 status = "okay";
28 };
29
30 tcsr@1949000 {
31 compatible = "qcom,tcsr";
32 reg = <0x1949000 0x100>;
33 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
34 };
35
36 tcsr@194b000 {
37 /* select hostmode */
38 compatible = "qcom,tcsr";
39 reg = <0x194b000 0x100>;
40 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
41 status = "okay";
42 };
43
44 ess_tcsr@1953000 {
45 compatible = "qcom,tcsr";
46 reg = <0x1953000 0x1000>;
47 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
48 };
49
50 tcsr@1957000 {
51 compatible = "qcom,tcsr";
52 reg = <0x1957000 0x100>;
53 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
54 };
55
56 crypto@8e3a000 {
57 status = "okay";
58 };
59 };
60
61 keys {
62 compatible = "gpio-keys";
63
64 wps {
65 label = "wps";
66 gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
67 linux,code = <KEY_WPS_BUTTON>;
68 };
69
70 reset {
71 label = "reset";
72 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
73 linux,code = <KEY_RESTART>;
74 };
75 };
76
77 leds {
78 compatible = "gpio-leds";
79
80 led_power: power {
81 function = LED_FUNCTION_POWER;
82 color = <LED_COLOR_ID_GREEN>;
83 gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
84 default-state = "on";
85 };
86
87 mesh {
88 label = "green:mesh";
89 gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
90 };
91
92 wlan {
93 function = LED_FUNCTION_WLAN;
94 color = <LED_COLOR_ID_GREEN>;
95 gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
96 linux,default-trigger = "phy0tpt";
97 };
98 };
99 };
100
101 &watchdog {
102 status = "okay";
103 };
104
105 &prng {
106 status = "okay";
107 };
108
109 &vqmmc {
110 status = "okay";
111 };
112
113 &sdhci {
114 status = "okay";
115 pinctrl-0 = <&sd_pins>;
116 pinctrl-names = "default";
117 cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
118 vqmmc-supply = <&vqmmc>;
119 };
120
121 &blsp_dma {
122 status = "okay";
123 };
124
125 &cryptobam {
126 status = "okay";
127 };
128
129 &blsp1_spi1 {
130 pinctrl-0 = <&spi_0_pins>;
131 pinctrl-names = "default";
132 status = "okay";
133 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
134
135 flash@0 {
136 compatible = "jedec,spi-nor";
137 reg = <0>;
138 spi-max-frequency = <24000000>;
139
140 partitions {
141 compatible = "fixed-partitions";
142 #address-cells = <1>;
143 #size-cells = <1>;
144
145 SBL1@0 {
146 label = "SBL1";
147 reg = <0x0 0x40000>;
148 read-only;
149 };
150
151 MIBIB@40000 {
152 label = "MIBIB";
153 reg = <0x40000 0x20000>;
154 read-only;
155 };
156
157 QSEE@60000 {
158 label = "QSEE";
159 reg = <0x60000 0x60000>;
160 read-only;
161 };
162
163 CDT@c0000 {
164 label = "CDT";
165 reg = <0xc0000 0x10000>;
166 read-only;
167 };
168
169 DDRPARAMS@d0000 {
170 label = "DDRPARAMS";
171 reg = <0xd0000 0x10000>;
172 read-only;
173 };
174
175 APPSBLENV@e0000 {
176 label = "APPSBLENV";
177 reg = <0xe0000 0x10000>;
178 read-only;
179 };
180
181 APPSBL@f0000 {
182 label = "APPSBL";
183 reg = <0xf0000 0x80000>;
184 read-only;
185 };
186
187 ART@170000 {
188 label = "ART";
189 reg = <0x170000 0x10000>;
190 read-only;
191
192 nvmem-layout {
193 compatible = "fixed-layout";
194 #address-cells = <1>;
195 #size-cells = <1>;
196
197 precal_art_1000: precal@1000 {
198 reg = <0x1000 0x2f20>;
199 };
200
201 precal_art_5000: precal@5000 {
202 reg = <0x5000 0x2f20>;
203 };
204 };
205 };
206
207 firmware@180000 {
208 compatible = "denx,fit";
209 label = "firmware";
210 reg = <0x180000 0xe80000>;
211 };
212 };
213 };
214 };
215
216 &blsp1_spi2 {
217 pinctrl-0 = <&spi_1_pins>;
218 pinctrl-names = "default";
219 status = "okay";
220
221 spidev1: spi@0 {
222 compatible = "silabs,si3210";
223 reg = <0>;
224 spi-max-frequency = <24000000>;
225 };
226 };
227
228 &blsp1_uart1 {
229 pinctrl-0 = <&serial_pins>;
230 pinctrl-names = "default";
231 status = "okay";
232 };
233
234 &blsp1_uart2 {
235 pinctrl-0 = <&serial_1_pins>;
236 pinctrl-names = "default";
237 status = "okay";
238 };
239
240 &tlmm {
241 serial_pins: serial_pinmux {
242 mux {
243 pins = "gpio16", "gpio17";
244 function = "blsp_uart0";
245 bias-disable;
246 };
247 };
248
249 serial_1_pins: serial1_pinmux {
250 mux {
251 pins = "gpio8", "gpio9",
252 "gpio10", "gpio11";
253 function = "blsp_uart1";
254 bias-disable;
255 };
256 };
257
258 spi_0_pins: spi_0_pinmux {
259 pinmux {
260 function = "blsp_spi0";
261 pins = "gpio13", "gpio14", "gpio15";
262 };
263 pinmux_cs {
264 function = "gpio";
265 pins = "gpio12";
266 };
267 pinconf {
268 pins = "gpio13", "gpio14", "gpio15";
269 drive-strength = <12>;
270 bias-disable;
271 };
272 pinconf_cs {
273 pins = "gpio12";
274 drive-strength = <2>;
275 bias-disable;
276 output-high;
277 };
278 };
279
280 spi_1_pins: spi_1_pinmux {
281 mux {
282 pins = "gpio44", "gpio46", "gpio47";
283 function = "blsp_spi1";
284 bias-disable;
285 };
286 host_int {
287 pins = "gpio42";
288 function = "gpio";
289 input;
290 };
291 cs {
292 pins = "gpio45";
293 function = "gpio";
294 bias-pull-up;
295 };
296 wake {
297 pins = "gpio40";
298 function = "gpio";
299 output-high;
300 };
301 reset {
302 pins = "gpio49";
303 function = "gpio";
304 output-high;
305 };
306 };
307
308 sd_pins: sd_pins {
309 pinmux {
310 function = "sdio";
311 pins = "gpio23", "gpio24", "gpio25", "gpio26",
312 "gpio28", "gpio29", "gpio30", "gpio31";
313 drive-strength = <10>;
314 };
315
316 pinmux_sd_clk {
317 function = "sdio";
318 pins = "gpio27";
319 drive-strength = <16>;
320 };
321
322 pinmux_sd7 {
323 function = "sdio";
324 pins = "gpio32";
325 drive-strength = <10>;
326 bias-disable;
327 };
328 };
329 };
330
331 &usb2_hs_phy {
332 status = "okay";
333 };
334
335 &usb2 {
336 status = "okay";
337 };
338
339 &usb3_hs_phy {
340 status = "okay";
341 };
342
343 &usb3_ss_phy {
344 status = "okay";
345 };
346
347 &usb3 {
348 status = "okay";
349 };
350
351 &wifi0 {
352 status = "okay";
353 nvmem-cell-names = "pre-calibration";
354 nvmem-cells = <&precal_art_1000>;
355 qcom,ath10k-calibration-variant = "GL-S1300";
356 };
357
358 &wifi1 {
359 status = "okay";
360 nvmem-cell-names = "pre-calibration";
361 nvmem-cells = <&precal_art_5000>;
362 qcom,ath10k-calibration-variant = "GL-S1300";
363 };