target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4029-insect-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for Meraki "Insect" series
   4  *
   5  * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
   6  * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
   7  *
   8  * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without
  12  * any warranty of any kind, whether express or implied.
  13  */
  14
  15 #include "qcom-ipq4019.dtsi"
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18 #include <dt-bindings/soc/qcom,tcsr.h>
  19 #include <dt-bindings/leds/common.h>
  20
  21 / {
  22         aliases {
  23                 led-boot = &status_green;
  24                 led-failsafe = &status_red;
  25                 led-running = &status_green;
  26                 led-upgrade = &power_orange;
  27         };
  28
  29         /* Do we really need this defined? */
  30         memory {
  31                 device_type = "memory";
  32                 reg = <0x80000000 0x10000000>;
  33         };
  34
  35         soc {
  36                 /* It is a 56-bit counter that supplies the count to the ARM arch
  37                    timers and without upstream driver */
  38                 counter@4a1000 {
  39                         compatible = "qcom,qca-gcnt";
  40                         reg = <0x4a1000 0x4>;
  41                 };
  42
  43                 ess_tcsr@1953000 {
  44                         compatible = "qcom,tcsr";
  45                         reg = <0x1953000 0x1000>;
  46                         qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
  47                 };
  48
  49                 tcsr@1949000 {
  50                         compatible = "qcom,tcsr";
  51                         reg = <0x1949000 0x100>;
  52                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  53                 };
  54
  55                 tcsr@1957000 {
  56                         compatible = "qcom,tcsr";
  57                         reg = <0x1957000 0x100>;
  58                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  59                 };
  60         };
  61
  62         keys {
  63                 compatible = "gpio-keys";
  64
  65                 reset {
  66                         label = "reset";
  67                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  68                         linux,code = <KEY_RESTART>;
  69                 };
  70         };
  71
  72         leds {
  73                 compatible = "gpio-leds";
  74
  75                 power_orange: power {
  76                         function = LED_FUNCTION_POWER;
  77                         color = <LED_COLOR_ID_ORANGE>;
  78                         gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
  79                         panic-indicator;
  80                 };
  81         };
  82 };
  83
  84 &watchdog {
  85         status = "okay";
  86 };
  87
  88 &prng {
  89         status = "okay";
  90 };
  91
  92 &crypto {
  93         status = "okay";
  94 };
  95
  96 &blsp_dma {
  97         status = "okay";
  98 };
  99
 100 &blsp1_uart1 {
 101         pinctrl-0 = <&serial_0_pins>;
 102         pinctrl-names = "default";
 103         status = "okay";
 104 };
 105
 106 &blsp1_uart2 {
 107         pinctrl-0 = <&serial_1_pins>;
 108         pinctrl-names = "default";
 109         status = "okay";
 110
 111         bluetooth {
 112                 compatible = "ti,cc2650";
 113                 enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
 114         };
 115 };
 116
 117 &cryptobam {
 118         status = "okay";
 119 };
 120
 121 &blsp1_i2c3 {
 122         pinctrl-0 = <&i2c_0_pins>;
 123         pinctrl-names = "default";
 124         status = "okay";
 125
 126         eeprom@50 {
 127                 compatible = "atmel,24c64";
 128                 pagesize = <32>;
 129                 reg = <0x50>;
 130                 read-only; /* This holds our MAC & Meraki board-data */
 131                 #address-cells = <1>;
 132                 #size-cells = <1>;
 133
 134                 mac_address: mac-address@66 {
 135                         compatible = "mac-base";
 136                         reg = <0x66 0x6>;
 137                         #nvmem-cell-cells = <1>;
 138                 };
 139         };
 140 };
 141
 142 &blsp1_i2c4 {
 143         pinctrl-0 = <&i2c_1_pins>;
 144         pinctrl-names = "default";
 145         status = "okay";
 146
 147         tricolor: led-controller@30 {
 148                 compatible = "ti,lp5562";
 149                 reg = <0x30>;
 150                 clock-mode = /bits/8 <2>;
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153
 154                 /* RGB led */
 155                 status_red: chan@0 {
 156                         chan-name = "red:status";
 157                         led-cur = /bits/ 8 <0x20>;
 158                         max-cur = /bits/ 8 <0x60>;
 159                         reg = <0>;
 160                         color = <LED_COLOR_ID_RED>;
 161                 };
 162
 163                 status_green: chan@1 {
 164                         chan-name = "green:status";
 165                         led-cur = /bits/ 8 <0x20>;
 166                         max-cur = /bits/ 8 <0x60>;
 167                         reg = <1>;
 168                         color = <LED_COLOR_ID_GREEN>;
 169                 };
 170
 171                 chan@2 {
 172                         chan-name = "blue:status";
 173                         led-cur = /bits/ 8 <0x20>;
 174                         max-cur = /bits/ 8 <0x60>;
 175                         reg = <2>;
 176                         color = <LED_COLOR_ID_BLUE>;
 177                 };
 178
 179                 chan@3 {
 180                         chan-name = "white:status";
 181                         led-cur = /bits/ 8 <0x20>;
 182                         max-cur = /bits/ 8 <0x60>;
 183                         reg = <3>;
 184                         color = <LED_COLOR_ID_WHITE>;
 185                 };
 186         };
 187 };
 188
 189 &nand {
 190         pinctrl-0 = <&nand_pins>;
 191         pinctrl-names = "default";
 192         status = "okay";
 193
 194         nand@0 {
 195                 partitions {
 196                         compatible = "fixed-partitions";
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199
 200                         partition@0 {
 201                                 label = "sbl1";
 202                                 reg = <0x00000000 0x00100000>;
 203                                 read-only;
 204                         };
 205                         partition@100000 {
 206                                 label = "mibib";
 207                                 reg = <0x00100000 0x00100000>;
 208                                 read-only;
 209                         };
 210                         partition@200000 {
 211                                 label = "bootconfig";
 212                                 reg = <0x00200000 0x00100000>;
 213                                 read-only;
 214                         };
 215                         partition@300000 {
 216                                 label = "qsee";
 217                                 reg = <0x00300000 0x00100000>;
 218                                 read-only;
 219                         };
 220                         partition@400000 {
 221                                 label = "qsee_alt";
 222                                 reg = <0x00400000 0x00100000>;
 223                                 read-only;
 224                         };
 225                         partition@500000 {
 226                                 label = "cdt";
 227                                 reg = <0x00500000 0x00080000>;
 228                                 read-only;
 229                         };
 230                         partition@580000 {
 231                                 label = "cdt_alt";
 232                                 reg = <0x00580000 0x00080000>;
 233                                 read-only;
 234                         };
 235                         partition@600000 {
 236                                 label = "ddrparams";
 237                                 reg = <0x00600000 0x00080000>;
 238                                 read-only;
 239                         };
 240                         partition@700000 {
 241                                 label = "u-boot";
 242                                 reg = <0x00700000 0x00200000>;
 243                                 read-only;
 244                         };
 245                         partition@900000 {
 246                                 label = "u-boot-backup";
 247                                 reg = <0x00900000 0x00200000>;
 248                                 read-only;
 249                         };
 250                         partition@b00000 {
 251                                 label = "ART";
 252                                 reg = <0x00b00000 0x00080000>;
 253                                 read-only;
 254                         };
 255                         partition@c00000 {
 256                                 label = "ubi";
 257                                 reg = <0x00c00000 0x07000000>;
 258                                 /*
 259                                  * Do not try to allocate the remaining
 260                                  * 4 MiB to this ubi partition. It will
 261                                  * confuse the u-boot and it might not
 262                                  * find the kernel partition anymore.
 263                                  */
 264                         };
 265                 };
 266         };
 267 };
 268
 269 &pcie0 {
 270         status = "okay";
 271         perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
 272         wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
 273
 274         bridge@0,0 {
 275                 reg = <0x00000000 0 0 0 0>;
 276                 #address-cells = <3>;
 277                 #size-cells = <2>;
 278                 ranges;
 279
 280                 wifi2: wifi@1,0 {
 281                         compatible = "qcom,ath10k";
 282                         status = "okay";
 283                         reg = <0x00010000 0 0 0 0>;
 284                         nvmem-cells = <&mac_address 1>;
 285                         nvmem-cell-names = "mac-address";
 286                 };
 287         };
 288 };
 289
 290 &qpic_bam {
 291         status = "okay";
 292 };
 293
 294 &tlmm {
 295         /*
 296          * GPIO43 should be 0/1 whenever the unit is
 297          * powered through PoE or AC-Adapter.
 298          * That said, playing with this seems to
 299          * reset the AP.
 300          */
 301
 302         mdio_pins: mdio_pinmux {
 303                 mux_1 {
 304                         pins = "gpio6";
 305                         function = "mdio";
 306                         bias-pull-up;
 307                 };
 308                 mux_2 {
 309                         pins = "gpio7";
 310                         function = "mdc";
 311                         bias-pull-up;
 312                 };
 313         };
 314
 315         serial_0_pins: serial_pinmux {
 316                 mux {
 317                         pins = "gpio16", "gpio17";
 318                         function = "blsp_uart0";
 319                         bias-disable;
 320                 };
 321         };
 322
 323         serial_1_pins: serial1_pinmux {
 324                 mux {
 325                         /* We use the i2c-0 pins for serial_1 */
 326                         pins = "gpio8", "gpio9";
 327                         function = "blsp_uart1";
 328                         bias-disable;
 329                 };
 330         };
 331
 332         i2c_0_pins: i2c_0_pinmux {
 333                 pinmux {
 334                         function = "blsp_i2c0";
 335                         pins = "gpio20", "gpio21";
 336                 };
 337                 pinconf {
 338                         pins = "gpio20", "gpio21";
 339                         drive-strength = <16>;
 340                         bias-disable;
 341                 };
 342         };
 343
 344         i2c_1_pins: i2c_1_pinmux {
 345                 pinmux {
 346                         function = "blsp_i2c1";
 347                         pins = "gpio34", "gpio35";
 348                 };
 349                 pinconf {
 350                         pins = "gpio34", "gpio35";
 351                         drive-strength = <16>;
 352                         bias-disable;
 353                 };
 354         };
 355
 356         nand_pins: nand_pins {
 357                 /*
 358                  * There are 18 pins. 15 pins are common between LCD and NAND.
 359                  * The QPIC controller arbitrates between LCD and NAND. Of the
 360                  * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
 361                  *
 362                  * The meraki source hints that the bluetooth module claims
 363                  * pin 52 as well. But sadly, there's no data whenever this
 364                  * is a NAND or LCD exclusive pin or not.
 365                  */
 366
 367                 pullups {
 368                         pins = "gpio52", "gpio53", "gpio58",
 369                                 "gpio59";
 370                         function = "qpic";
 371                         bias-pull-up;
 372                 };
 373
 374                 pulldowns {
 375                         pins = "gpio54", "gpio55", "gpio56",
 376                                 "gpio57", "gpio60", "gpio61",
 377                                 "gpio62", "gpio63", "gpio64",
 378                                 "gpio65", "gpio66", "gpio67",
 379                                 "gpio68", "gpio69";
 380                         function = "qpic";
 381                         bias-pull-down;
 382                 };
 383         };
 384 };
 385
 386 &wifi0 {
 387         status = "okay";
 388         qcom,ath10k-calibration-variant = "Meraki-MR33";
 389         nvmem-cells = <&mac_address 2>;
 390         nvmem-cell-names = "mac-address";
 391 };
 392
 393 &wifi1 {
 394         status = "okay";
 395         qcom,ath10k-calibration-variant = "Meraki-MR33";
 396         nvmem-cells = <&mac_address 3>;
 397         nvmem-cell-names = "mac-address";
 398 };
 399
 400 &mdio {
 401         status = "okay";
 402         pinctrl-0 = <&mdio_pins>;
 403         pinctrl-names = "default";
 404
 405         ar8035: ethernet-phy@1 {
 406                 reg = <1>;
 407         };
 408 };
 409
 410 &gmac {
 411         status = "okay";
 412         nvmem-cells = <&mac_address 0>;
 413         nvmem-cell-names = "mac-address";
 414 };
 415
 416 &switch {
 417         status = "okay";
 418
 419         /delete-property/ psgmii-ethphy;
 420 };
 421
 422 &swport5 {
 423         status = "okay";
 424
 425         label = "lan";
 426         phy-handle = <&ar8035>;
 427         phy-mode = "rgmii-rxid";
 428 };
 429
 430 &qca807x {
 431         status = "disabled";
 432 };
 433
 434 &ethphy0 {
 435         status = "disabled";
 436 };
 437
 438 &ethphy1 {
 439         status = "disabled";
 440 };
 441
 442 &ethphy2 {
 443         status = "disabled";
 444 };
 445
 446 &ethphy3 {
 447         status = "disabled";
 448 };
 449
 450 &ethphy4 {
 451         status = "disabled";
 452 };
 453
 454 &psgmiiphy {
 455         status = "disabled";
 456 };