1 From 544af73985cd14b450bb8e8a6c22b89a555ac729 Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Mon, 23 Jul 2018 09:10:35 +0200
4 Subject: [PATCH 6/8] qcom: ipq4019: add cpu operating points for cpufreq
7 This adds some operating points for cpu frequeny scaling
9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
10 Signed-off-by: John Crispin <john@phrozen.org>
12 arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
13 1 file changed, 26 insertions(+), 8 deletions(-)
15 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
16 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
19 clocks = <&gcc GCC_APPS_CLK_SRC>;
20 clock-frequency = <0>;
21 - operating-points = <
22 - /* kHz uV (fixed) */
28 - clock-latency = <256000>;
29 + operating-points-v2 = <&cpu0_opp_table>;
35 clocks = <&gcc GCC_APPS_CLK_SRC>;
36 clock-frequency = <0>;
37 + operating-points-v2 = <&cpu0_opp_table>;
43 clocks = <&gcc GCC_APPS_CLK_SRC>;
44 clock-frequency = <0>;
45 + operating-points-v2 = <&cpu0_opp_table>;
51 clocks = <&gcc GCC_APPS_CLK_SRC>;
52 clock-frequency = <0>;
53 + operating-points-v2 = <&cpu0_opp_table>;
61 + cpu0_opp_table: opp_table0 {
62 + compatible = "operating-points-v2";
66 + opp-hz = /bits/ 64 <48000000>;
67 + clock-latency-ns = <256000>;
70 + opp-hz = /bits/ 64 <200000000>;
71 + clock-latency-ns = <256000>;
74 + opp-hz = /bits/ 64 <500000000>;
75 + clock-latency-ns = <256000>;
78 + opp-hz = /bits/ 64 <716000000>;
79 + clock-latency-ns = <256000>;
84 compatible = "arm,cortex-a7-pmu";
85 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |