target/linux/ipq40xx/patches-4.14/077-qcom-ipq4019-add-USB-devicetree-nodes.patch

   1 From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 24 Jul 2018 14:47:55 +0200
   4 Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes
   5
   6 This patch makes USB work on the Dakota EVB.
   7
   8 Signed-off-by: John Crispin <john@phrozen.org>
   9 ---
  10  arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
  11  arch/arm/boot/dts/qcom-ipq4019.dtsi           | 74 +++++++++++++++++++++++++++
  12  2 files changed, 94 insertions(+)
  13
  14 diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
  15 index 418f9a022336..2ee5f05d5a43 100644
  16 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
  17 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
  18 @@ -109,5 +109,25 @@
  19                 wifi@a800000 {
  20                         status = "ok";
  21                 };
  22 +
  23 +               usb3_ss_phy: ssphy@9a000 {
  24 +                       status = "ok";
  25 +               };
  26 +
  27 +               usb3_hs_phy: hsphy@a6000 {
  28 +                       status = "ok";
  29 +               };
  30 +
  31 +               usb3: usb3@8af8800 {
  32 +                       status = "ok";
  33 +               };
  34 +
  35 +               usb2_hs_phy: hsphy@a8000 {
  36 +                       status = "ok";
  37 +               };
  38 +
  39 +               usb2: usb2@60f8800 {
  40 +                       status = "ok";
  41 +               };
  42         };
  43  };
  44 diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  45 index e5e52adbd5a3..e6b12129f0e4 100644
  46 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  47 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  48 @@ -553,5 +553,79 @@
  49                                           "legacy";
  50                         status = "disabled";
  51                 };
  52 +
  53 +               usb3_ss_phy: ssphy@9a000 {
  54 +                       compatible = "qcom,usb-ss-ipq4019-phy";
  55 +                       #phy-cells = <0>;
  56 +                       reg = <0x9a000 0x800>;
  57 +                       reg-names = "phy_base";
  58 +                       resets = <&gcc USB3_UNIPHY_PHY_ARES>;
  59 +                       reset-names = "por_rst";
  60 +                       status = "disabled";
  61 +               };
  62 +
  63 +               usb3_hs_phy: hsphy@a6000 {
  64 +                       compatible = "qcom,usb-hs-ipq4019-phy";
  65 +                       #phy-cells = <0>;
  66 +                       reg = <0xa6000 0x40>;
  67 +                       reg-names = "phy_base";
  68 +                       resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
  69 +                       reset-names = "por_rst", "srif_rst";
  70 +                       status = "disabled";
  71 +               };
  72 +
  73 +               usb3@8af8800 {
  74 +                       compatible = "qcom,dwc3";
  75 +                       reg = <0x8af8800 0x100>;
  76 +                       #address-cells = <1>;
  77 +                       #size-cells = <1>;
  78 +                       clocks = <&gcc GCC_USB3_MASTER_CLK>,
  79 +                                <&gcc GCC_USB3_SLEEP_CLK>,
  80 +                                <&gcc GCC_USB3_MOCK_UTMI_CLK>;
  81 +                       clock-names = "master", "sleep", "mock_utmi";
  82 +                       ranges;
  83 +                       status = "disabled";
  84 +
  85 +                       dwc3@8a00000 {
  86 +                               compatible = "snps,dwc3";
  87 +                               reg = <0x8a00000 0xf8000>;
  88 +                               interrupts = <0 132 0>;
  89 +                               phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
  90 +                               phy-names = "usb2-phy", "usb3-phy";
  91 +                               dr_mode = "host";
  92 +                       };
  93 +               };
  94 +
  95 +               usb2_hs_phy: hsphy@a8000 {
  96 +                       compatible = "qcom,usb-hs-ipq4019-phy";
  97 +                       #phy-cells = <0>;
  98 +                       reg = <0xa8000 0x40>;
  99 +                       reg-names = "phy_base";
 100 +                       resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
 101 +                       reset-names = "por_rst", "srif_rst";
 102 +                       status = "disabled";
 103 +               };
 104 +
 105 +               usb2@60f8800 {
 106 +                       compatible = "qcom,dwc3";
 107 +                       reg = <0x60f8800 0x100>;
 108 +                       #address-cells = <1>;
 109 +                       #size-cells = <1>;
 110 +                       clocks = <&gcc GCC_USB2_MASTER_CLK>,
 111 +                                <&gcc GCC_USB2_SLEEP_CLK>,
 112 +                                <&gcc GCC_USB2_MOCK_UTMI_CLK>;
 113 +                       clock-names = "master", "sleep", "mock_utmi";
 114 +                       ranges;
 115 +                       status = "disabled";
 116 +
 117 +                       dwc3@6000000 {
 118 +                               compatible = "snps,dwc3";
 119 +                               reg = <0x6000000 0xf8000>;
 120 +                               interrupts = <0 136 0>;
 121 +                               phys = <&usb2_hs_phy>;
 122 +                               phy-names = "usb2-phy";
 123 +                               dr_mode = "host";
 124 +                       };
 125 +               };
 126         };
 127  };
 128 --
 129 2.11.0
 130