1 From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Thu, 17 Mar 2016 16:22:28 -0500
4 Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
6 This adds the SoC nodes to the ipq4019 device tree and
7 enable it for the DK01.1 board.
9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
10 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
13 - replaced space with tab
14 - added sleep and mock_utmi clocks
15 - added registers for usb2 and usb3 parent node
16 - changed compatible to qca,ipa4019-dwc3
17 - updated usb2 and usb3 names
18 (included the reg - in case they become necessary later)
20 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
21 arch/arm/boot/dts/qcom-ipq4019.dtsi | 71 +++++++++++++++++++++++++++
22 2 files changed, 91 insertions(+)
24 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
25 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
31 + usb3_ss_phy: ssphy@9a000 {
35 + usb3_hs_phy: hsphy@a6000 {
39 + usb3: usb3@8af8800 {
43 + usb2_hs_phy: hsphy@a8000 {
47 + usb2: usb2@60f8800 {
52 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
53 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
59 + usb3_ss_phy: ssphy@9a000 {
60 + compatible = "qcom,usb-ss-ipq4019-phy";
62 + reg = <0x9a000 0x800>;
63 + reg-names = "phy_base";
64 + resets = <&gcc USB3_UNIPHY_PHY_ARES>;
65 + reset-names = "por_rst";
66 + status = "disabled";
69 + usb3_hs_phy: hsphy@a6000 {
70 + compatible = "qcom,usb-hs-ipq4019-phy";
72 + reg = <0xa6000 0x40>;
73 + reg-names = "phy_base";
74 + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
75 + reset-names = "por_rst", "srif_rst";
76 + status = "disabled";
80 + compatible = "qcom,dwc3";
81 + reg = <0x8af8800 0x100>;
82 + #address-cells = <1>;
84 + clocks = <&gcc GCC_USB3_MASTER_CLK>,
85 + <&gcc GCC_USB3_SLEEP_CLK>,
86 + <&gcc GCC_USB3_MOCK_UTMI_CLK>;
87 + clock-names = "master", "sleep", "mock_utmi";
89 + status = "disabled";
92 + compatible = "snps,dwc3";
93 + reg = <0x8a00000 0xf8000>;
94 + interrupts = <0 132 0>;
95 + phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
96 + phy-names = "usb2-phy", "usb3-phy";
101 + usb2_hs_phy: hsphy@a8000 {
102 + compatible = "qcom,usb-hs-ipq4019-phy";
104 + reg = <0xa8000 0x40>;
105 + reg-names = "phy_base";
106 + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
107 + reset-names = "por_rst", "srif_rst";
108 + status = "disabled";
112 + compatible = "qcom,dwc3";
113 + reg = <0x60f8800 0x100>;
114 + #address-cells = <1>;
116 + clocks = <&gcc GCC_USB2_MASTER_CLK>,
117 + <&gcc GCC_USB2_SLEEP_CLK>,
118 + <&gcc GCC_USB2_MOCK_UTMI_CLK>;
119 + clock-names = "master", "sleep", "mock_utmi";
121 + status = "disabled";
124 + compatible = "snps,dwc3";
125 + reg = <0x6000000 0xf8000>;
126 + interrupts = <0 136 0>;
127 + phys = <&usb2_hs_phy>;
128 + phy-names = "usb2-phy";
134 --- a/drivers/phy/qualcomm/Kconfig
135 +++ b/drivers/phy/qualcomm/Kconfig
136 @@ -8,6 +8,13 @@ config PHY_QCOM_APQ8064_SATA
140 +config PHY_QCOM_IPQ4019_USB
141 + tristate "Qualcomm IPQ4019 USB PHY module"
142 + depends on OF && ARCH_QCOM
145 + Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
147 config PHY_QCOM_IPQ806X_SATA
148 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
150 --- a/drivers/phy/qualcomm/Makefile
151 +++ b/drivers/phy/qualcomm/Makefile
153 # SPDX-License-Identifier: GPL-2.0
154 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
155 +obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
156 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
157 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
158 obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
160 +++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
163 + * Copyright (C) 2018 John Crispin <john@phrozen.org>
165 + * Based on code from
166 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
168 + * This program is free software; you can redistribute it and/or modify
169 + * it under the terms of the GNU General Public License as published by
170 + * the Free Software Foundation; either version 2 of the License, or
171 + * (at your option) any later version.
173 + * This program is distributed in the hope that it will be useful,
174 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
175 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
176 + * GNU General Public License for more details.
179 +#include <linux/delay.h>
180 +#include <linux/err.h>
181 +#include <linux/io.h>
182 +#include <linux/kernel.h>
183 +#include <linux/module.h>
184 +#include <linux/mutex.h>
185 +#include <linux/of_platform.h>
186 +#include <linux/phy/phy.h>
187 +#include <linux/platform_device.h>
188 +#include <linux/reset.h>
191 + * Magic registers copied from the SDK driver code
193 +#define PHY_CTRL0_ADDR 0x000
194 +#define PHY_CTRL1_ADDR 0x004
195 +#define PHY_CTRL2_ADDR 0x008
196 +#define PHY_CTRL3_ADDR 0x00C
197 +#define PHY_CTRL4_ADDR 0x010
198 +#define PHY_MISC_ADDR 0x024
199 +#define PHY_IPG_ADDR 0x030
201 +#define PHY_CTRL0_VAL 0xA4600015
202 +#define PHY_CTRL1_VAL 0x09500000
203 +#define PHY_CTRL2_VAL 0x00058180
204 +#define PHY_CTRL3_VAL 0x6DB6DCD6
205 +#define PHY_CTRL4_VAL 0x836DB6DB
206 +#define PHY_MISC_VAL 0x3803FB0C
207 +#define PHY_IPG_VAL 0x47323232
209 +struct ipq4019_usb_phy {
210 + struct device *dev;
212 + void __iomem *base;
213 + struct reset_control *por_rst;
214 + struct reset_control *srif_rst;
217 +static int ipq4019_ss_phy_power_off(struct phy *_phy)
219 + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
221 + reset_control_assert(phy->por_rst);
227 +static int ipq4019_ss_phy_power_on(struct phy *_phy)
229 + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
231 + ipq4019_ss_phy_power_off(_phy);
233 + reset_control_deassert(phy->por_rst);
238 +static struct phy_ops ipq4019_usb_ss_phy_ops = {
239 + .power_on = ipq4019_ss_phy_power_on,
240 + .power_off = ipq4019_ss_phy_power_off,
243 +static int ipq4019_hs_phy_power_off(struct phy *_phy)
245 + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
247 + reset_control_assert(phy->por_rst);
250 + reset_control_assert(phy->srif_rst);
256 +static int ipq4019_hs_phy_power_on(struct phy *_phy)
258 + struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
260 + ipq4019_hs_phy_power_off(_phy);
262 + reset_control_deassert(phy->srif_rst);
265 + writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
266 + writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
267 + writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
268 + writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
269 + writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
270 + writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
271 + writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
274 + reset_control_deassert(phy->por_rst);
279 +static struct phy_ops ipq4019_usb_hs_phy_ops = {
280 + .power_on = ipq4019_hs_phy_power_on,
281 + .power_off = ipq4019_hs_phy_power_off,
284 +static const struct of_device_id ipq4019_usb_phy_of_match[] = {
285 + { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops},
286 + { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops},
289 +MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match);
291 +static int ipq4019_usb_phy_probe(struct platform_device *pdev)
293 + struct device *dev = &pdev->dev;
294 + struct resource *res;
295 + struct phy_provider *phy_provider;
296 + struct ipq4019_usb_phy *phy;
297 + const struct of_device_id *match;
299 + match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev);
303 + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
307 + phy->dev = &pdev->dev;
308 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
309 + phy->base = devm_ioremap_resource(&pdev->dev, res);
310 + if (IS_ERR(phy->base)) {
311 + dev_err(dev, "failed to remap register memory\n");
312 + return PTR_ERR(phy->base);
315 + phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
316 + if (IS_ERR(phy->por_rst)) {
317 + if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER)
318 + dev_err(dev, "POR reset is missing\n");
319 + return PTR_ERR(phy->por_rst);
322 + phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst");
323 + if (IS_ERR(phy->srif_rst))
324 + return PTR_ERR(phy->srif_rst);
326 + phy->phy = devm_phy_create(dev, NULL, match->data);
327 + if (IS_ERR(phy->phy)) {
328 + dev_err(dev, "failed to create PHY\n");
329 + return PTR_ERR(phy->phy);
331 + phy_set_drvdata(phy->phy, phy);
333 + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
335 + return PTR_ERR_OR_ZERO(phy_provider);
338 +static struct platform_driver ipq4019_usb_phy_driver = {
339 + .probe = ipq4019_usb_phy_probe,
341 + .of_match_table = ipq4019_usb_phy_of_match,
342 + .name = "ipq4019-usb-phy",
345 +module_platform_driver(ipq4019_usb_phy_driver);
347 +MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver");
348 +MODULE_AUTHOR("John Crispin <john@phrozen.org>");
349 +MODULE_LICENSE("GPL v2");