target/linux/ipq40xx/patches-4.19/700-net-add-qualcomm-mdio.patch

   1 From 234d6f40fb4b771b396b45a9492aab463771bd0b Mon Sep 17 00:00:00 2001
   2 From: Kristian Evensen <kristian.evensen@gmail.com>
   3 Date: Tue, 6 Aug 2019 11:42:57 +0200
   4 Subject: [PATCH] phy: Add ipq40xx mdio driver
   5
   6 ---
   7  drivers/net/phy/Kconfig        |   7 +
   8  drivers/net/phy/Makefile       |   1 +
   9  drivers/net/phy/mdio-ipq40xx.c | 247 +++++++++++++++++++++++++++++++++
  10  3 files changed, 255 insertions(+)
  11  create mode 100644 drivers/net/phy/mdio-ipq40xx.c
  12
  13 --- a/drivers/net/phy/Kconfig
  14 +++ b/drivers/net/phy/Kconfig
  15 @@ -519,6 +519,13 @@ config XILINX_GMII2RGMII
  16           the Reduced Gigabit Media Independent Interface(RGMII) between
  17           Ethernet physical media devices and the Gigabit Ethernet controller.
  18
  19 +config MDIO_IPQ40XX
  20 +       tristate "Qualcomm Atheros ipq40xx MDIO interface"
  21 +       depends on HAS_IOMEM && OF
  22 +       ---help---
  23 +         This driver supports the MDIO interface found in Qualcomm
  24 +         Atheros ipq40xx Soc chip.
  25 +
  26  endif # PHYLIB
  27
  28  config MICREL_KS8995MA
  29 --- a/drivers/net/phy/Makefile
  30 +++ b/drivers/net/phy/Makefile
  31 @@ -48,6 +48,7 @@ obj-$(CONFIG_MDIO_CAVIUM)     += mdio-cavium
  32  obj-$(CONFIG_MDIO_GPIO)                += mdio-gpio.o
  33  obj-$(CONFIG_MDIO_HISI_FEMAC)  += mdio-hisi-femac.o
  34  obj-$(CONFIG_MDIO_I2C)         += mdio-i2c.o
  35 +obj-$(CONFIG_MDIO_IPQ40XX)     += mdio-ipq40xx.o
  36  obj-$(CONFIG_MDIO_MOXART)      += mdio-moxart.o
  37  obj-$(CONFIG_MDIO_MSCC_MIIM)   += mdio-mscc-miim.o
  38  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  39 --- /dev/null
  40 +++ b/drivers/net/phy/mdio-ipq40xx.c
  41 @@ -0,0 +1,247 @@
  42 +/*
  43 + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
  44 + *
  45 + * Permission to use, copy, modify, and/or distribute this software for
  46 + * any purpose with or without fee is hereby granted, provided that the
  47 + * above copyright notice and this permission notice appear in all copies.
  48 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  49 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  50 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  51 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  52 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  53 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
  54 + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  55 + */
  56 +
  57 +#include <linux/delay.h>
  58 +#include <linux/kernel.h>
  59 +#include <linux/module.h>
  60 +#include <linux/mutex.h>
  61 +#include <linux/io.h>
  62 +#include <linux/of_address.h>
  63 +#include <linux/of_mdio.h>
  64 +#include <linux/of_gpio.h>
  65 +#include <linux/phy.h>
  66 +#include <linux/platform_device.h>
  67 +#include <linux/gpio.h>
  68 +
  69 +#define MDIO_CTRL_0_REG                0x40
  70 +#define MDIO_CTRL_1_REG                0x44
  71 +#define MDIO_CTRL_2_REG                0x48
  72 +#define MDIO_CTRL_3_REG                0x4c
  73 +#define MDIO_CTRL_4_REG                0x50
  74 +#define MDIO_CTRL_4_ACCESS_BUSY                BIT(16)
  75 +#define MDIO_CTRL_4_ACCESS_START               BIT(8)
  76 +#define MDIO_CTRL_4_ACCESS_CODE_READ           0
  77 +#define MDIO_CTRL_4_ACCESS_CODE_WRITE  1
  78 +#define CTRL_0_REG_DEFAULT_VALUE       0x150FF
  79 +
  80 +#define IPQ40XX_MDIO_RETRY     1000
  81 +#define IPQ40XX_MDIO_DELAY     10
  82 +
  83 +struct ipq40xx_mdio_data {
  84 +       struct mii_bus  *mii_bus;
  85 +       void __iomem    *membase;
  86 +       struct device   *dev;
  87 +};
  88 +
  89 +static int ipq40xx_mdio_wait_busy(struct ipq40xx_mdio_data *am)
  90 +{
  91 +       int i;
  92 +
  93 +       for (i = 0; i < IPQ40XX_MDIO_RETRY; i++) {
  94 +               unsigned int busy;
  95 +
  96 +               busy = readl(am->membase + MDIO_CTRL_4_REG) &
  97 +                       MDIO_CTRL_4_ACCESS_BUSY;
  98 +               if (!busy)
  99 +                       return 0;
 100 +
 101 +               /* BUSY might take to be cleard by 15~20 times of loop */
 102 +               udelay(IPQ40XX_MDIO_DELAY);
 103 +       }
 104 +
 105 +       dev_err(am->dev, "%s: MDIO operation timed out\n", am->mii_bus->name);
 106 +
 107 +       return -ETIMEDOUT;
 108 +}
 109 +
 110 +static int ipq40xx_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 111 +{
 112 +       struct ipq40xx_mdio_data *am = bus->priv;
 113 +       int value = 0;
 114 +       unsigned int cmd = 0;
 115 +
 116 +       lockdep_assert_held(&bus->mdio_lock);
 117 +
 118 +       if (ipq40xx_mdio_wait_busy(am))
 119 +               return -ETIMEDOUT;
 120 +
 121 +       /* issue the phy address and reg */
 122 +       writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
 123 +
 124 +       cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_READ;
 125 +
 126 +       /* issue read command */
 127 +       writel(cmd, am->membase + MDIO_CTRL_4_REG);
 128 +
 129 +       /* Wait read complete */
 130 +       if (ipq40xx_mdio_wait_busy(am))
 131 +               return -ETIMEDOUT;
 132 +
 133 +       /* Read data */
 134 +       value = readl(am->membase + MDIO_CTRL_3_REG);
 135 +
 136 +       return value;
 137 +}
 138 +
 139 +static int ipq40xx_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
 140 +                           u16 value)
 141 +{
 142 +       struct ipq40xx_mdio_data *am = bus->priv;
 143 +       unsigned int cmd = 0;
 144 +
 145 +       lockdep_assert_held(&bus->mdio_lock);
 146 +
 147 +       if (ipq40xx_mdio_wait_busy(am))
 148 +               return -ETIMEDOUT;
 149 +
 150 +       /* issue the phy address and reg */
 151 +       writel((mii_id << 8) | regnum, am->membase + MDIO_CTRL_1_REG);
 152 +
 153 +       /* issue write data */
 154 +       writel(value, am->membase + MDIO_CTRL_2_REG);
 155 +
 156 +       cmd = MDIO_CTRL_4_ACCESS_START|MDIO_CTRL_4_ACCESS_CODE_WRITE;
 157 +       /* issue write command */
 158 +       writel(cmd, am->membase + MDIO_CTRL_4_REG);
 159 +
 160 +       /* Wait write complete */
 161 +       if (ipq40xx_mdio_wait_busy(am))
 162 +               return -ETIMEDOUT;
 163 +
 164 +       return 0;
 165 +}
 166 +
 167 +static int ipq40xx_phy_reset(struct platform_device *pdev)
 168 +{
 169 +       struct device_node *mdio_node;
 170 +       int phy_reset_gpio_number;
 171 +       int ret;
 172 +
 173 +       mdio_node = of_find_node_by_name(NULL, "mdio");
 174 +       if (!mdio_node) {
 175 +               dev_err(&pdev->dev, "Could not find mdio node\n");
 176 +               return 0;
 177 +       }
 178 +
 179 +       ret = of_get_named_gpio(mdio_node, "phy-reset-gpio", 0);
 180 +       if (ret < 0) {
 181 +               dev_err(&pdev->dev, "Could not find phy-reset-gpio\n");
 182 +               return 0;
 183 +       }
 184 +
 185 +       phy_reset_gpio_number = ret;
 186 +
 187 +       ret = gpio_request(phy_reset_gpio_number, "phy-reset-gpio");
 188 +       if (ret) {
 189 +               dev_err(&pdev->dev, "Can't get phy-reset-gpio %d\n", ret);
 190 +               return ret;
 191 +       }
 192 +
 193 +       ret = gpio_direction_output(phy_reset_gpio_number, 0x0);
 194 +       if (ret) {
 195 +               dev_err(&pdev->dev,
 196 +                       "Can't set direction for phy-reset-gpio %d\n", ret);
 197 +               goto phy_reset_out;
 198 +       }
 199 +
 200 +       usleep_range(1000, 10005);
 201 +
 202 +       gpio_set_value(phy_reset_gpio_number, 0x01);
 203 +
 204 +phy_reset_out:
 205 +       gpio_free(phy_reset_gpio_number);
 206 +
 207 +       return ret;
 208 +}
 209 +
 210 +static int ipq40xx_mdio_probe(struct platform_device *pdev)
 211 +{
 212 +       struct ipq40xx_mdio_data *am;
 213 +       struct resource *res;
 214 +       int i, ret;
 215 +
 216 +       ret = ipq40xx_phy_reset(pdev);
 217 +       if (ret) {
 218 +               dev_err(&pdev->dev, "Could not find qca8075 reset gpio\n");
 219 +               return -ENODEV;
 220 +       }
 221 +
 222 +       am = devm_kzalloc(&pdev->dev, sizeof(*am), GFP_KERNEL);
 223 +       if (!am)
 224 +               return -ENOMEM;
 225 +
 226 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 227 +       if (!res) {
 228 +               dev_err(&pdev->dev, "no iomem resource found\n");
 229 +               return -ENXIO;
 230 +       }
 231 +
 232 +       am->membase = devm_ioremap_resource(&pdev->dev, res);
 233 +       if (IS_ERR(am->membase)) {
 234 +               dev_err(&pdev->dev, "unable to ioremap registers\n");
 235 +               return PTR_ERR(am->membase);
 236 +       }
 237 +
 238 +       am->mii_bus = devm_mdiobus_alloc(&pdev->dev);
 239 +       if (!am->mii_bus)
 240 +               return  -ENOMEM;
 241 +
 242 +       writel(CTRL_0_REG_DEFAULT_VALUE, am->membase + MDIO_CTRL_0_REG);
 243 +
 244 +       am->mii_bus->name = "ipq40xx_mdio";
 245 +       am->mii_bus->read = ipq40xx_mdio_read;
 246 +       am->mii_bus->write = ipq40xx_mdio_write;
 247 +       am->mii_bus->priv = am;
 248 +       am->mii_bus->parent = &pdev->dev;
 249 +       snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
 250 +
 251 +       am->dev = &pdev->dev;
 252 +       platform_set_drvdata(pdev, am);
 253 +
 254 +       return of_mdiobus_register(am->mii_bus, pdev->dev.of_node);
 255 +}
 256 +
 257 +static int ipq40xx_mdio_remove(struct platform_device *pdev)
 258 +{
 259 +       struct ipq40xx_mdio_data *am = platform_get_drvdata(pdev);
 260 +
 261 +       mdiobus_unregister(am->mii_bus);
 262 +
 263 +       return 0;
 264 +}
 265 +
 266 +static const struct of_device_id ipq40xx_mdio_dt_ids[] = {
 267 +       { .compatible = "qcom,ipq4019-mdio" },
 268 +       { }
 269 +};
 270 +MODULE_DEVICE_TABLE(of, ipq40xx_mdio_dt_ids);
 271 +
 272 +static struct platform_driver ipq40xx_mdio_driver = {
 273 +       .probe = ipq40xx_mdio_probe,
 274 +       .remove = ipq40xx_mdio_remove,
 275 +       .driver = {
 276 +               .name = "ipq40xx-mdio",
 277 +               .of_match_table = ipq40xx_mdio_dt_ids,
 278 +       },
 279 +};
 280 +
 281 +module_platform_driver(ipq40xx_mdio_driver);
 282 +
 283 +#define DRV_VERSION     "1.0"
 284 +
 285 +MODULE_DESCRIPTION("IPQ40XX MDIO interface driver");
 286 +MODULE_AUTHOR("Qualcomm Atheros");
 287 +MODULE_VERSION(DRV_VERSION);
 288 +MODULE_LICENSE("Dual BSD/GPL");