target/linux/ipq40xx/patches-5.10/0003-v5.6-ARM-dts-qcom-Add-nodes-for-SMP-boot-in-IPQ40xx.patch

   1 From 5e4548922009870a38bcf1d887317676d4e08f54 Mon Sep 17 00:00:00 2001
   2 From: Damir Franusic <damir.franusic@sartura.hr>
   3 Date: Thu, 21 Nov 2019 16:29:02 +0100
   4 Subject: [PATCH] ARM: dts: qcom: Add nodes for SMP boot in IPQ40xx
   5
   6 Add missing nodes and properties to enable SMP
   7 support on IPQ40xx devices.
   8
   9 Booting without "saw_l2" node:
  10
  11 [    0.001400] CPU: Testing write buffer coherency: ok
  12 [    0.001856] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
  13 [    0.060163] Setting up static identity map for 0x80300000 - 0x80300060
  14 [    0.080140] rcu: Hierarchical SRCU implementation.
  15 [    0.120258] smp: Bringing up secondary CPUs ...
  16 [    0.200540] CPU1: failed to boot: -19
  17 [    0.280689] CPU2: failed to boot: -19
  18 [    0.360874] CPU3: failed to boot: -19
  19 [    0.360966] smp: Brought up 1 node, 1 CPU
  20 [    0.360979] SMP: Total of 1 processors activated (96.00 BogoMIPS).
  21 [    0.360988] CPU: All CPU(s) started in SVC mode.
  22
  23 Then, booting with "saw_l2" node present (this patch applied):
  24
  25 [    0.001450] CPU: Testing write buffer coherency: ok
  26 [    0.001904] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
  27 [    0.060161] Setting up static identity map for 0x80300000 - 0x80300060
  28 [    0.080137] rcu: Hierarchical SRCU implementation.
  29 [    0.120252] smp: Bringing up secondary CPUs ...
  30 [    0.200958] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
  31 [    0.281091] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
  32 [    0.361264] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
  33 [    0.361430] smp: Brought up 1 node, 4 CPUs
  34 [    0.361460] SMP: Total of 4 processors activated (384.00 BogoMIPS).
  35 [    0.361469] CPU: All CPU(s) started in SVC mode.
  36
  37 Signed-off-by: Damir Franusic <damir.franusic@sartura.hr>
  38 Cc: Luka Perkov <luka.perkov@sartura.hr>
  39 Cc: Robert Marko <robert.marko@sartura.hr>
  40 Cc: Andy Gross <agross@kernel.org>
  41 Cc: Rob Herring <robh+dt@kernel.org>
  42 Cc: linux-arm-msm@vger.kernel.org
  43 Link: https://lore.kernel.org/r/20191121152902.21394-1-damir.franusic@gmail.com
  44 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  45 ---
  46  arch/arm/boot/dts/qcom-ipq4019.dtsi | 7 +++++++
  47  1 file changed, 7 insertions(+)
  48
  49 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  50 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  51 @@ -102,6 +102,7 @@
  52                 L2: l2-cache {
  53                         compatible = "cache";
  54                         cache-level = <2>;
  55 +                       qcom,saw = <&saw_l2>;
  56                 };
  57         };
  58
  59 @@ -353,6 +354,12 @@
  60                         regulator;
  61                 };
  62
  63 +               saw_l2: regulator@b012000 {
  64 +                       compatible = "qcom,saw2";
  65 +                       reg = <0xb012000 0x1000>;
  66 +                       regulator;
  67 +               };
  68 +
  69                 blsp1_uart1: serial@78af000 {
  70                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  71                         reg = <0x78af000 0x200>;