1 From 44327d7098d4f32c24ec8c528e5aff6e030956bc Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robert.marko@sartura.hr>
3 Date: Wed, 20 Oct 2021 13:21:45 +0200
4 Subject: [PATCH] arm: dts: ipq4019: add ethernet controller DT node
6 Since IPQ40xx SoC built-in ethernet controller now has a driver,
7 add its DT node so it can be used.
9 Signed-off-by: Robert Marko <robert.marko@sartura.hr>
11 arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
12 1 file changed, 48 insertions(+)
14 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
15 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
28 + gmac: ethernet@c080000 {
29 + compatible = "qcom,ipq4019-ess-edma";
30 + reg = <0xc080000 0x8000>;
31 + resets = <&gcc ESS_RESET>;
32 + reset-names = "ess_rst";
33 + clocks = <&gcc GCC_ESS_CLK>;
34 + clock-names = "ess_clk";
35 + interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
36 + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
37 + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
38 + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
39 + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
40 + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
41 + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
42 + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
43 + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
44 + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
45 + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
46 + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
47 + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
48 + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
49 + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
50 + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
51 + <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
52 + <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
53 + <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
54 + <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
55 + <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
56 + <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
57 + <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
58 + <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
59 + <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
60 + <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
61 + <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
62 + <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
63 + <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
64 + <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
65 + <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
66 + <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
68 + status = "disabled";
70 + phy-mode = "internal";