target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch

   1 From 157ac9f52fd9b9a22cf12f7755a905fb34ef72f7 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <j4g8y7@gmail.com>
   3 Date: Fri, 25 Dec 2020 08:02:47 +0100
   4 Subject: [PATCH] net: phy: define PSGMII PHY interface mode
   5
   6 The PSGMII interface is similar to QSGMII. The main difference
   7 is that the PSGMII interface combines five SGMII lines into a
   8 single link while in QSGMII only four lines are combined.
   9
  10 Similarly to the QSGMII, this interface mode might also needs
  11 special handling within the MAC driver.
  12
  13 Add definitions for the PHY layer to allow to express this type
  14 of connection between the MAC and PHY.
  15
  16 Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
  17 ---
  18  Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
  19  drivers/net/phy/phylink.c                                      | 2 ++
  20  include/linux/phy.h                                            | 3 +++
  21  3 files changed, 6 insertions(+)
  22
  23 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
  24 +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
  25 @@ -64,6 +64,7 @@ properties:
  26        - mii
  27        - gmii
  28        - sgmii
  29 +      - psgmii
  30        - qsgmii
  31        - tbi
  32        - rev-mii
  33 --- a/drivers/net/phy/phy-core.c
  34 +++ b/drivers/net/phy/phy-core.c
  35 @@ -140,6 +140,8 @@ int phy_interface_num_ports(phy_interfac
  36         case PHY_INTERFACE_MODE_QSGMII:
  37         case PHY_INTERFACE_MODE_QUSGMII:
  38                 return 4;
  39 +       case PHY_INTERFACE_MODE_PSGMII:
  40 +               return 5;
  41         case PHY_INTERFACE_MODE_MAX:
  42                 WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode");
  43                 return 0;
  44 --- a/drivers/net/phy/phylink.c
  45 +++ b/drivers/net/phy/phylink.c
  46 @@ -371,6 +371,7 @@ void phylink_get_linkmodes(unsigned long
  47         case PHY_INTERFACE_MODE_RGMII_RXID:
  48         case PHY_INTERFACE_MODE_RGMII_ID:
  49         case PHY_INTERFACE_MODE_RGMII:
  50 +       case PHY_INTERFACE_MODE_PSGMII:
  51         case PHY_INTERFACE_MODE_QSGMII:
  52         case PHY_INTERFACE_MODE_QUSGMII:
  53         case PHY_INTERFACE_MODE_SGMII:
  54 @@ -636,6 +637,7 @@ static int phylink_parse_mode(struct phy
  55
  56                 switch (pl->link_config.interface) {
  57                 case PHY_INTERFACE_MODE_SGMII:
  58 +               case PHY_INTERFACE_MODE_PSGMII:
  59                 case PHY_INTERFACE_MODE_QSGMII:
  60                 case PHY_INTERFACE_MODE_QUSGMII:
  61                         phylink_set(pl->supported, 10baseT_Half);
  62 --- a/include/linux/phy.h
  63 +++ b/include/linux/phy.h
  64 @@ -141,6 +141,7 @@ typedef enum {
  65         PHY_INTERFACE_MODE_XGMII,
  66         PHY_INTERFACE_MODE_XLGMII,
  67         PHY_INTERFACE_MODE_MOCA,
  68 +       PHY_INTERFACE_MODE_PSGMII,
  69         PHY_INTERFACE_MODE_QSGMII,
  70         PHY_INTERFACE_MODE_TRGMII,
  71         PHY_INTERFACE_MODE_100BASEX,
  72 @@ -248,6 +249,8 @@ static inline const char *phy_modes(phy_
  73                 return "xlgmii";
  74         case PHY_INTERFACE_MODE_MOCA:
  75                 return "moca";
  76 +       case PHY_INTERFACE_MODE_PSGMII:
  77 +               return "psgmii";
  78         case PHY_INTERFACE_MODE_QSGMII:
  79                 return "qsgmii";
  80         case PHY_INTERFACE_MODE_TRGMII: