target/linux/ipq40xx/patches-5.4/0005-01-v5.8-net-phy-mdio-add-IPQ4019-MDIO-driver.patch

   1 From 466ed24fb22342f3ae1c10758a6a0c6a8c081b2d Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robert.marko@sartura.hr>
   3 Date: Thu, 30 Apr 2020 11:07:05 +0200
   4 Subject: [PATCH] net: phy: mdio: add IPQ4019 MDIO driver
   5
   6 This patch adds the driver for the MDIO interface
   7 inside of Qualcomm IPQ40xx series SoC-s.
   8
   9 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  10 Signed-off-by: Robert Marko <robert.marko@sartura.hr>
  11 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  12 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  13 Cc: Luka Perkov <luka.perkov@sartura.hr>
  14 Signed-off-by: David S. Miller <davem@davemloft.net>
  15 ---
  16  drivers/net/phy/Kconfig        |   7 ++
  17  drivers/net/phy/Makefile       |   1 +
  18  drivers/net/phy/mdio-ipq4019.c | 160 +++++++++++++++++++++++++++++++++
  19  3 files changed, 168 insertions(+)
  20  create mode 100644 drivers/net/phy/mdio-ipq4019.c
  21
  22 --- a/drivers/net/phy/Kconfig
  23 +++ b/drivers/net/phy/Kconfig
  24 @@ -156,6 +156,13 @@ config MDIO_I2C
  25
  26           This is library mode.
  27
  28 +config MDIO_IPQ4019
  29 +       tristate "Qualcomm IPQ4019 MDIO interface support"
  30 +       depends on HAS_IOMEM && OF_MDIO
  31 +       help
  32 +         This driver supports the MDIO interface found in Qualcomm
  33 +         IPQ40xx series Soc-s.
  34 +
  35  config MDIO_MOXART
  36         tristate "MOXA ART MDIO interface support"
  37         depends on ARCH_MOXART || COMPILE_TEST
  38 --- a/drivers/net/phy/Makefile
  39 +++ b/drivers/net/phy/Makefile
  40 @@ -50,6 +50,7 @@ obj-$(CONFIG_MDIO_CAVIUM)     += mdio-cavium
  41  obj-$(CONFIG_MDIO_GPIO)                += mdio-gpio.o
  42  obj-$(CONFIG_MDIO_HISI_FEMAC)  += mdio-hisi-femac.o
  43  obj-$(CONFIG_MDIO_I2C)         += mdio-i2c.o
  44 +obj-$(CONFIG_MDIO_IPQ4019)     += mdio-ipq4019.o
  45  obj-$(CONFIG_MDIO_MOXART)      += mdio-moxart.o
  46  obj-$(CONFIG_MDIO_MSCC_MIIM)   += mdio-mscc-miim.o
  47  obj-$(CONFIG_MDIO_OCTEON)      += mdio-octeon.o
  48 --- /dev/null
  49 +++ b/drivers/net/phy/mdio-ipq4019.c
  50 @@ -0,0 +1,160 @@
  51 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  52 +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. */
  53 +/* Copyright (c) 2020 Sartura Ltd. */
  54 +
  55 +#include <linux/delay.h>
  56 +#include <linux/kernel.h>
  57 +#include <linux/module.h>
  58 +#include <linux/io.h>
  59 +#include <linux/iopoll.h>
  60 +#include <linux/of_address.h>
  61 +#include <linux/of_mdio.h>
  62 +#include <linux/phy.h>
  63 +#include <linux/platform_device.h>
  64 +
  65 +#define MDIO_ADDR_REG                          0x44
  66 +#define MDIO_DATA_WRITE_REG                    0x48
  67 +#define MDIO_DATA_READ_REG                     0x4c
  68 +#define MDIO_CMD_REG                           0x50
  69 +#define MDIO_CMD_ACCESS_BUSY           BIT(16)
  70 +#define MDIO_CMD_ACCESS_START          BIT(8)
  71 +#define MDIO_CMD_ACCESS_CODE_READ      0
  72 +#define MDIO_CMD_ACCESS_CODE_WRITE     1
  73 +
  74 +#define ipq4019_MDIO_TIMEOUT   10000
  75 +#define ipq4019_MDIO_SLEEP             10
  76 +
  77 +struct ipq4019_mdio_data {
  78 +       void __iomem    *membase;
  79 +};
  80 +
  81 +static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
  82 +{
  83 +       struct ipq4019_mdio_data *priv = bus->priv;
  84 +       unsigned int busy;
  85 +
  86 +       return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy,
  87 +                                 (busy & MDIO_CMD_ACCESS_BUSY) == 0,
  88 +                                 ipq4019_MDIO_SLEEP, ipq4019_MDIO_TIMEOUT);
  89 +}
  90 +
  91 +static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  92 +{
  93 +       struct ipq4019_mdio_data *priv = bus->priv;
  94 +       unsigned int cmd;
  95 +
  96 +       /* Reject clause 45 */
  97 +       if (regnum & MII_ADDR_C45)
  98 +               return -EOPNOTSUPP;
  99 +
 100 +       if (ipq4019_mdio_wait_busy(bus))
 101 +               return -ETIMEDOUT;
 102 +
 103 +       /* issue the phy address and reg */
 104 +       writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
 105 +
 106 +       cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
 107 +
 108 +       /* issue read command */
 109 +       writel(cmd, priv->membase + MDIO_CMD_REG);
 110 +
 111 +       /* Wait read complete */
 112 +       if (ipq4019_mdio_wait_busy(bus))
 113 +               return -ETIMEDOUT;
 114 +
 115 +       /* Read and return data */
 116 +       return readl(priv->membase + MDIO_DATA_READ_REG);
 117 +}
 118 +
 119 +static int ipq4019_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
 120 +                                                        u16 value)
 121 +{
 122 +       struct ipq4019_mdio_data *priv = bus->priv;
 123 +       unsigned int cmd;
 124 +
 125 +       /* Reject clause 45 */
 126 +       if (regnum & MII_ADDR_C45)
 127 +               return -EOPNOTSUPP;
 128 +
 129 +       if (ipq4019_mdio_wait_busy(bus))
 130 +               return -ETIMEDOUT;
 131 +
 132 +       /* issue the phy address and reg */
 133 +       writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
 134 +
 135 +       /* issue write data */
 136 +       writel(value, priv->membase + MDIO_DATA_WRITE_REG);
 137 +
 138 +       cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
 139 +       /* issue write command */
 140 +       writel(cmd, priv->membase + MDIO_CMD_REG);
 141 +
 142 +       /* Wait write complete */
 143 +       if (ipq4019_mdio_wait_busy(bus))
 144 +               return -ETIMEDOUT;
 145 +
 146 +       return 0;
 147 +}
 148 +
 149 +static int ipq4019_mdio_probe(struct platform_device *pdev)
 150 +{
 151 +       struct ipq4019_mdio_data *priv;
 152 +       struct mii_bus *bus;
 153 +       int ret;
 154 +
 155 +       bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
 156 +       if (!bus)
 157 +               return -ENOMEM;
 158 +
 159 +       priv = bus->priv;
 160 +
 161 +       priv->membase = devm_platform_ioremap_resource(pdev, 0);
 162 +       if (IS_ERR(priv->membase))
 163 +               return PTR_ERR(priv->membase);
 164 +
 165 +       bus->name = "ipq4019_mdio";
 166 +       bus->read = ipq4019_mdio_read;
 167 +       bus->write = ipq4019_mdio_write;
 168 +       bus->parent = &pdev->dev;
 169 +       snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id);
 170 +
 171 +       ret = of_mdiobus_register(bus, pdev->dev.of_node);
 172 +       if (ret) {
 173 +               dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
 174 +               return ret;
 175 +       }
 176 +
 177 +       platform_set_drvdata(pdev, bus);
 178 +
 179 +       return 0;
 180 +}
 181 +
 182 +static int ipq4019_mdio_remove(struct platform_device *pdev)
 183 +{
 184 +       struct mii_bus *bus = platform_get_drvdata(pdev);
 185 +
 186 +       mdiobus_unregister(bus);
 187 +
 188 +       return 0;
 189 +}
 190 +
 191 +static const struct of_device_id ipq4019_mdio_dt_ids[] = {
 192 +       { .compatible = "qcom,ipq4019-mdio" },
 193 +       { }
 194 +};
 195 +MODULE_DEVICE_TABLE(of, ipq4019_mdio_dt_ids);
 196 +
 197 +static struct platform_driver ipq4019_mdio_driver = {
 198 +       .probe = ipq4019_mdio_probe,
 199 +       .remove = ipq4019_mdio_remove,
 200 +       .driver = {
 201 +               .name = "ipq4019-mdio",
 202 +               .of_match_table = ipq4019_mdio_dt_ids,
 203 +       },
 204 +};
 205 +
 206 +module_platform_driver(ipq4019_mdio_driver);
 207 +
 208 +MODULE_DESCRIPTION("ipq4019 MDIO interface driver");
 209 +MODULE_AUTHOR("Qualcomm Atheros");
 210 +MODULE_LICENSE("Dual BSD/GPL");