1 From 59e056cda4beb5412e3653e6360c2eb0fa770baa Mon Sep 17 00:00:00 2001
2 From: Eneas U de Queiroz <cotequeiroz@gmail.com>
3 Date: Fri, 20 Dec 2019 16:02:18 -0300
4 Subject: [PATCH 07/11] crypto: qce - allow building only hashes/ciphers
6 Allow the user to choose whether to build support for all algorithms
7 (default), hashes-only, or skciphers-only.
9 The QCE engine does not appear to scale as well as the CPU to handle
10 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
11 QCE handles only 2 requests in parallel.
13 Ipsec throughput seems to improve when disabling either family of
14 algorithms, sharing the load with the CPU. Enabling skciphers-only
17 Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
18 Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
21 --- a/drivers/crypto/Kconfig
22 +++ b/drivers/crypto/Kconfig
23 @@ -616,6 +616,14 @@ config CRYPTO_DEV_QCE
24 tristate "Qualcomm crypto engine accelerator"
25 depends on ARCH_QCOM || COMPILE_TEST
28 + This driver supports Qualcomm crypto engine accelerator
29 + hardware. To compile this driver as a module, choose M here. The
30 + module will be called qcrypto.
32 +config CRYPTO_DEV_QCE_SKCIPHER
34 + depends on CRYPTO_DEV_QCE
38 @@ -623,10 +631,57 @@ config CRYPTO_DEV_QCE
41 select CRYPTO_BLKCIPHER
43 +config CRYPTO_DEV_QCE_SHA
45 + depends on CRYPTO_DEV_QCE
48 + prompt "Algorithms enabled for QCE acceleration"
49 + default CRYPTO_DEV_QCE_ENABLE_ALL
50 + depends on CRYPTO_DEV_QCE
52 - This driver supports Qualcomm crypto engine accelerator
53 - hardware. To compile this driver as a module, choose M here. The
54 - module will be called qcrypto.
55 + This option allows to choose whether to build support for all algorihtms
56 + (default), hashes-only, or skciphers-only.
58 + The QCE engine does not appear to scale as well as the CPU to handle
59 + multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
60 + QCE handles only 2 requests in parallel.
62 + Ipsec throughput seems to improve when disabling either family of
63 + algorithms, sharing the load with the CPU. Enabling skciphers-only
64 + appears to work best.
66 + config CRYPTO_DEV_QCE_ENABLE_ALL
67 + bool "All supported algorithms"
68 + select CRYPTO_DEV_QCE_SKCIPHER
69 + select CRYPTO_DEV_QCE_SHA
71 + Enable all supported algorithms:
72 + - AES (CBC, CTR, ECB, XTS)
76 + - SHA256, HMAC-SHA256
78 + config CRYPTO_DEV_QCE_ENABLE_SKCIPHER
79 + bool "Symmetric-key ciphers only"
80 + select CRYPTO_DEV_QCE_SKCIPHER
82 + Enable symmetric-key ciphers only:
83 + - AES (CBC, CTR, ECB, XTS)
87 + config CRYPTO_DEV_QCE_ENABLE_SHA
88 + bool "Hash/HMAC only"
89 + select CRYPTO_DEV_QCE_SHA
91 + Enable hashes/HMAC algorithms only:
93 + - SHA256, HMAC-SHA256
97 config CRYPTO_DEV_QCE_SW_MAX_LEN
98 int "Default maximum request size to use software for AES"
99 --- a/drivers/crypto/qce/Makefile
100 +++ b/drivers/crypto/qce/Makefile
102 obj-$(CONFIG_CRYPTO_DEV_QCE) += qcrypto.o
103 qcrypto-objs := core.o \
110 +qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SHA) += sha.o
111 +qcrypto-$(CONFIG_CRYPTO_DEV_QCE_SKCIPHER) += skcipher.o
112 --- a/drivers/crypto/qce/common.c
113 +++ b/drivers/crypto/qce/common.c
114 @@ -43,52 +43,56 @@ qce_clear_array(struct qce_device *qce,
115 qce_write(qce, offset + i * sizeof(u32), 0);
118 -static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
119 +static u32 qce_config_reg(struct qce_device *qce, int little)
122 + u32 beats = (qce->burst_size >> 3) - 1;
123 + u32 pipe_pair = qce->pipe_pair_id;
126 - if (IS_AES(flags)) {
127 - if (aes_key_size == AES_KEYSIZE_128)
128 - cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
129 - else if (aes_key_size == AES_KEYSIZE_256)
130 - cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
132 + config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
133 + config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
134 + BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
135 + config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
136 + config &= ~HIGH_SPD_EN_N_SHIFT;
139 - cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
140 - else if (IS_DES(flags) || IS_3DES(flags))
141 - cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
143 + config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
146 - cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
150 - if (IS_3DES(flags))
151 - cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
152 +void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
158 - switch (flags & QCE_MODE_MASK) {
160 - cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
163 - cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
166 - cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
169 - cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
172 - cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
173 - cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
177 + n = len / sizeof(u32);
178 + for (; n > 0; n--) {
179 + *d = cpu_to_be32p((const __u32 *) s);
180 + s += sizeof(__u32);
186 +static void qce_setup_config(struct qce_device *qce)
190 + /* get big endianness */
191 + config = qce_config_reg(qce, 0);
194 + qce_write(qce, REG_STATUS, 0);
195 + qce_write(qce, REG_CONFIG, config);
198 +static inline void qce_crypto_go(struct qce_device *qce)
200 + qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
203 +#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
204 static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
207 @@ -135,88 +139,6 @@ static u32 qce_auth_cfg(unsigned long fl
211 -static u32 qce_config_reg(struct qce_device *qce, int little)
213 - u32 beats = (qce->burst_size >> 3) - 1;
214 - u32 pipe_pair = qce->pipe_pair_id;
217 - config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK;
218 - config |= BIT(MASK_DOUT_INTR_SHIFT) | BIT(MASK_DIN_INTR_SHIFT) |
219 - BIT(MASK_OP_DONE_INTR_SHIFT) | BIT(MASK_ERR_INTR_SHIFT);
220 - config |= (pipe_pair << PIPE_SET_SELECT_SHIFT) & PIPE_SET_SELECT_MASK;
221 - config &= ~HIGH_SPD_EN_N_SHIFT;
224 - config |= BIT(LITTLE_ENDIAN_MODE_SHIFT);
229 -void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len)
235 - n = len / sizeof(u32);
236 - for (; n > 0; n--) {
237 - *d = cpu_to_be32p((const __u32 *) s);
238 - s += sizeof(__u32);
243 -static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
245 - u8 swap[QCE_AES_IV_LENGTH];
248 - if (ivsize > QCE_AES_IV_LENGTH)
251 - memset(swap, 0, QCE_AES_IV_LENGTH);
253 - for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
254 - i < QCE_AES_IV_LENGTH; i++, j--)
257 - qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
260 -static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
261 - unsigned int enckeylen, unsigned int cryptlen)
263 - u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
264 - unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
265 - unsigned int xtsdusize;
267 - qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
269 - qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
271 - /* xts du size 512B */
272 - xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
273 - qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
276 -static void qce_setup_config(struct qce_device *qce)
280 - /* get big endianness */
281 - config = qce_config_reg(qce, 0);
284 - qce_write(qce, REG_STATUS, 0);
285 - qce_write(qce, REG_CONFIG, config);
288 -static inline void qce_crypto_go(struct qce_device *qce)
290 - qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
293 static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
294 u32 totallen, u32 offset)
296 @@ -301,6 +223,87 @@ go_proc:
302 +#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
303 +static u32 qce_encr_cfg(unsigned long flags, u32 aes_key_size)
307 + if (IS_AES(flags)) {
308 + if (aes_key_size == AES_KEYSIZE_128)
309 + cfg |= ENCR_KEY_SZ_AES128 << ENCR_KEY_SZ_SHIFT;
310 + else if (aes_key_size == AES_KEYSIZE_256)
311 + cfg |= ENCR_KEY_SZ_AES256 << ENCR_KEY_SZ_SHIFT;
315 + cfg |= ENCR_ALG_AES << ENCR_ALG_SHIFT;
316 + else if (IS_DES(flags) || IS_3DES(flags))
317 + cfg |= ENCR_ALG_DES << ENCR_ALG_SHIFT;
320 + cfg |= ENCR_KEY_SZ_DES << ENCR_KEY_SZ_SHIFT;
322 + if (IS_3DES(flags))
323 + cfg |= ENCR_KEY_SZ_3DES << ENCR_KEY_SZ_SHIFT;
325 + switch (flags & QCE_MODE_MASK) {
327 + cfg |= ENCR_MODE_ECB << ENCR_MODE_SHIFT;
330 + cfg |= ENCR_MODE_CBC << ENCR_MODE_SHIFT;
333 + cfg |= ENCR_MODE_CTR << ENCR_MODE_SHIFT;
336 + cfg |= ENCR_MODE_XTS << ENCR_MODE_SHIFT;
339 + cfg |= ENCR_MODE_CCM << ENCR_MODE_SHIFT;
340 + cfg |= LAST_CCM_XFR << LAST_CCM_SHIFT;
349 +static void qce_xts_swapiv(__be32 *dst, const u8 *src, unsigned int ivsize)
351 + u8 swap[QCE_AES_IV_LENGTH];
354 + if (ivsize > QCE_AES_IV_LENGTH)
357 + memset(swap, 0, QCE_AES_IV_LENGTH);
359 + for (i = (QCE_AES_IV_LENGTH - ivsize), j = ivsize - 1;
360 + i < QCE_AES_IV_LENGTH; i++, j--)
363 + qce_cpu_to_be32p_array(dst, swap, QCE_AES_IV_LENGTH);
366 +static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
367 + unsigned int enckeylen, unsigned int cryptlen)
369 + u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
370 + unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
371 + unsigned int xtsdusize;
373 + qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
375 + qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
377 + /* xts du size 512B */
378 + xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);
379 + qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
382 static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
383 u32 totallen, u32 offset)
384 @@ -382,15 +385,20 @@ static int qce_setup_regs_skcipher(struc
390 int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
394 +#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
395 case CRYPTO_ALG_TYPE_SKCIPHER:
396 return qce_setup_regs_skcipher(async_req, totallen, offset);
398 +#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
399 case CRYPTO_ALG_TYPE_AHASH:
400 return qce_setup_regs_ahash(async_req, totallen, offset);
405 --- a/drivers/crypto/qce/core.c
406 +++ b/drivers/crypto/qce/core.c
408 #define QCE_QUEUE_LENGTH 1
410 static const struct qce_algo_ops *qce_ops[] = {
411 +#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
414 +#ifdef CONFIG_CRYPTO_DEV_QCE_SHA
419 static void qce_unregister_algs(struct qce_device *qce)