1 --- a/drivers/net/phy/Kconfig
2 +++ b/drivers/net/phy/Kconfig
3 @@ -526,6 +526,13 @@ config MDIO_IPQ40XX
4 This driver supports the MDIO interface found in Qualcomm
5 Atheros ipq40xx Soc chip.
8 + tristate "Driver for Qualcomm Atheros IPQ40XX switches"
9 + depends on HAS_IOMEM && OF
12 + This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
16 config MICREL_KS8995MA
17 --- a/drivers/net/phy/Makefile
18 +++ b/drivers/net/phy/Makefile
19 @@ -62,6 +62,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
21 obj-$(CONFIG_AMD_PHY) += amd.o
22 obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
23 +obj-$(CONFIG_AR40XX_PHY) += ar40xx.o
24 obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
25 obj-$(CONFIG_AT803X_PHY) += at803x.o
26 obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o
28 +++ b/drivers/net/phy/ar40xx.c
31 + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
33 + * Permission to use, copy, modify, and/or distribute this software for
34 + * any purpose with or without fee is hereby granted, provided that the
35 + * above copyright notice and this permission notice appear in all copies.
36 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
37 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
38 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
39 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
40 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
41 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
42 + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
45 +#include <linux/module.h>
46 +#include <linux/list.h>
47 +#include <linux/bitops.h>
48 +#include <linux/switch.h>
49 +#include <linux/delay.h>
50 +#include <linux/phy.h>
51 +#include <linux/clk.h>
52 +#include <linux/reset.h>
53 +#include <linux/lockdep.h>
54 +#include <linux/workqueue.h>
55 +#include <linux/of_device.h>
56 +#include <linux/of_address.h>
57 +#include <linux/mdio.h>
58 +#include <linux/gpio.h>
62 +static struct ar40xx_priv *ar40xx_priv;
64 +#define MIB_DESC(_s , _o, _n) \
71 +static const struct ar40xx_mib_desc ar40xx_mibs[] = {
72 + MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"),
73 + MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"),
74 + MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"),
75 + MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"),
76 + MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"),
77 + MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"),
78 + MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"),
79 + MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"),
80 + MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"),
81 + MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"),
82 + MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"),
83 + MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"),
84 + MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"),
85 + MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"),
86 + MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"),
87 + MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"),
88 + MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"),
89 + MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"),
90 + MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"),
91 + MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"),
92 + MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"),
93 + MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"),
94 + MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"),
95 + MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"),
96 + MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"),
97 + MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"),
98 + MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"),
99 + MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"),
100 + MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"),
101 + MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"),
102 + MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"),
103 + MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"),
104 + MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"),
105 + MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"),
106 + MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"),
107 + MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"),
108 + MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"),
109 + MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"),
110 + MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"),
114 +ar40xx_read(struct ar40xx_priv *priv, int reg)
116 + return readl(priv->hw_addr + reg);
120 +ar40xx_psgmii_read(struct ar40xx_priv *priv, int reg)
122 + return readl(priv->psgmii_hw_addr + reg);
126 +ar40xx_write(struct ar40xx_priv *priv, int reg, u32 val)
128 + writel(val, priv->hw_addr + reg);
132 +ar40xx_rmw(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
136 + ret = ar40xx_read(priv, reg);
139 + ar40xx_write(priv, reg, ret);
144 +ar40xx_psgmii_write(struct ar40xx_priv *priv, int reg, u32 val)
146 + writel(val, priv->psgmii_hw_addr + reg);
150 +ar40xx_phy_dbg_write(struct ar40xx_priv *priv, int phy_addr,
151 + u16 dbg_addr, u16 dbg_data)
153 + struct mii_bus *bus = priv->mii_bus;
155 + mutex_lock(&bus->mdio_lock);
156 + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
157 + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA, dbg_data);
158 + mutex_unlock(&bus->mdio_lock);
162 +ar40xx_phy_dbg_read(struct ar40xx_priv *priv, int phy_addr,
163 + u16 dbg_addr, u16 *dbg_data)
165 + struct mii_bus *bus = priv->mii_bus;
167 + mutex_lock(&bus->mdio_lock);
168 + bus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);
169 + *dbg_data = bus->read(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA);
170 + mutex_unlock(&bus->mdio_lock);
174 +ar40xx_phy_mmd_write(struct ar40xx_priv *priv, u32 phy_id,
175 + u16 mmd_num, u16 reg_id, u16 reg_val)
177 + struct mii_bus *bus = priv->mii_bus;
179 + mutex_lock(&bus->mdio_lock);
180 + bus->write(bus, phy_id,
181 + AR40XX_MII_ATH_MMD_ADDR, mmd_num);
182 + bus->write(bus, phy_id,
183 + AR40XX_MII_ATH_MMD_DATA, reg_id);
184 + bus->write(bus, phy_id,
185 + AR40XX_MII_ATH_MMD_ADDR,
187 + bus->write(bus, phy_id,
188 + AR40XX_MII_ATH_MMD_DATA, reg_val);
189 + mutex_unlock(&bus->mdio_lock);
193 +ar40xx_phy_mmd_read(struct ar40xx_priv *priv, u32 phy_id,
194 + u16 mmd_num, u16 reg_id)
197 + struct mii_bus *bus = priv->mii_bus;
199 + mutex_lock(&bus->mdio_lock);
200 + bus->write(bus, phy_id,
201 + AR40XX_MII_ATH_MMD_ADDR, mmd_num);
202 + bus->write(bus, phy_id,
203 + AR40XX_MII_ATH_MMD_DATA, reg_id);
204 + bus->write(bus, phy_id,
205 + AR40XX_MII_ATH_MMD_ADDR,
207 + value = bus->read(bus, phy_id, AR40XX_MII_ATH_MMD_DATA);
208 + mutex_unlock(&bus->mdio_lock);
212 +/* Start of swconfig support */
215 +ar40xx_phy_poll_reset(struct ar40xx_priv *priv)
217 + u32 i, in_reset, retries = 500;
218 + struct mii_bus *bus = priv->mii_bus;
220 + /* Assume RESET was recently issued to some or all of the phys */
221 + in_reset = GENMASK(AR40XX_NUM_PHYS - 1, 0);
223 + while (retries--) {
224 + /* 1ms should be plenty of time.
225 + * 802.3 spec allows for a max wait time of 500ms
227 + usleep_range(1000, 2000);
229 + for (i = 0; i < AR40XX_NUM_PHYS; i++) {
232 + /* skip devices which have completed reset */
233 + if (!(in_reset & BIT(i)))
236 + val = mdiobus_read(bus, i, MII_BMCR);
240 + /* mark when phy is no longer in reset state */
241 + if (!(val & BMCR_RESET))
242 + in_reset &= ~BIT(i);
249 + dev_warn(&bus->dev, "Failed to reset all phys! (in_reset: 0x%x)\n",
254 +ar40xx_phy_init(struct ar40xx_priv *priv)
257 + struct mii_bus *bus;
260 + bus = priv->mii_bus;
261 + for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
262 + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
263 + val &= ~AR40XX_PHY_MANU_CTRL_EN;
264 + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
265 + mdiobus_write(bus, i,
266 + MII_ADVERTISE, ADVERTISE_ALL |
267 + ADVERTISE_PAUSE_CAP |
268 + ADVERTISE_PAUSE_ASYM);
269 + mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
270 + mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
273 + ar40xx_phy_poll_reset(priv);
277 +ar40xx_port_phy_linkdown(struct ar40xx_priv *priv)
279 + struct mii_bus *bus;
283 + bus = priv->mii_bus;
284 + for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
285 + mdiobus_write(bus, i, MII_CTRL1000, 0);
286 + mdiobus_write(bus, i, MII_ADVERTISE, 0);
287 + mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
288 + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);
289 + val |= AR40XX_PHY_MANU_CTRL_EN;
290 + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);
291 + /* disable transmit */
292 + ar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_2, &val);
294 + ar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_2, val);
299 +ar40xx_set_mirror_regs(struct ar40xx_priv *priv)
303 + /* reset all mirror registers */
304 + ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
305 + AR40XX_FWD_CTRL0_MIRROR_PORT,
306 + (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
307 + for (port = 0; port < AR40XX_NUM_PORTS; port++) {
308 + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(port),
309 + AR40XX_PORT_LOOKUP_ING_MIRROR_EN, 0);
311 + ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(port),
312 + AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN, 0);
315 + /* now enable mirroring if necessary */
316 + if (priv->source_port >= AR40XX_NUM_PORTS ||
317 + priv->monitor_port >= AR40XX_NUM_PORTS ||
318 + priv->source_port == priv->monitor_port) {
322 + ar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,
323 + AR40XX_FWD_CTRL0_MIRROR_PORT,
324 + (priv->monitor_port << AR40XX_FWD_CTRL0_MIRROR_PORT_S));
326 + if (priv->mirror_rx)
327 + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(priv->source_port), 0,
328 + AR40XX_PORT_LOOKUP_ING_MIRROR_EN);
330 + if (priv->mirror_tx)
331 + ar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(priv->source_port),
332 + 0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN);
336 +ar40xx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
338 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
339 + u8 ports = priv->vlan_table[val->port_vlan];
343 + for (i = 0; i < dev->ports; i++) {
344 + struct switch_port *p;
346 + if (!(ports & BIT(i)))
349 + p = &val->value.ports[val->len++];
351 + if ((priv->vlan_tagged & BIT(i)) ||
352 + (priv->pvid[i] != val->port_vlan))
353 + p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
361 +ar40xx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
363 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
364 + u8 *vt = &priv->vlan_table[val->port_vlan];
368 + for (i = 0; i < val->len; i++) {
369 + struct switch_port *p = &val->value.ports[i];
371 + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
372 + if (val->port_vlan == priv->pvid[p->id])
373 + priv->vlan_tagged |= BIT(p->id);
375 + priv->vlan_tagged &= ~BIT(p->id);
376 + priv->pvid[p->id] = val->port_vlan;
385 +ar40xx_reg_wait(struct ar40xx_priv *priv, u32 reg, u32 mask, u32 val,
390 + for (i = 0; i < timeout; i++) {
393 + t = ar40xx_read(priv, reg);
394 + if ((t & mask) == val)
397 + usleep_range(1000, 2000);
404 +ar40xx_mib_op(struct ar40xx_priv *priv, u32 op)
408 + lockdep_assert_held(&priv->mib_lock);
410 + /* Capture the hardware statistics for all ports */
411 + ar40xx_rmw(priv, AR40XX_REG_MIB_FUNC,
412 + AR40XX_MIB_FUNC, (op << AR40XX_MIB_FUNC_S));
414 + /* Wait for the capturing to complete. */
415 + ret = ar40xx_reg_wait(priv, AR40XX_REG_MIB_FUNC,
416 + AR40XX_MIB_BUSY, 0, 10);
422 +ar40xx_mib_fetch_port_stat(struct ar40xx_priv *priv, int port, bool flush)
427 + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
429 + WARN_ON(port >= priv->dev.ports);
431 + lockdep_assert_held(&priv->mib_lock);
433 + base = AR40XX_REG_PORT_STATS_START +
434 + AR40XX_REG_PORT_STATS_LEN * port;
436 + mib_stats = &priv->mib_stats[port * num_mibs];
440 + len = num_mibs * sizeof(*mib_stats);
441 + memset(mib_stats, 0, len);
444 + for (i = 0; i < num_mibs; i++) {
445 + const struct ar40xx_mib_desc *mib;
448 + mib = &ar40xx_mibs[i];
449 + t = ar40xx_read(priv, base + mib->offset);
450 + if (mib->size == 2) {
453 + hi = ar40xx_read(priv, base + mib->offset + 4);
462 +ar40xx_mib_capture(struct ar40xx_priv *priv)
464 + return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_CAPTURE);
468 +ar40xx_mib_flush(struct ar40xx_priv *priv)
470 + return ar40xx_mib_op(priv, AR40XX_MIB_FUNC_FLUSH);
474 +ar40xx_sw_set_reset_mibs(struct switch_dev *dev,
475 + const struct switch_attr *attr,
476 + struct switch_val *val)
478 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
481 + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
483 + mutex_lock(&priv->mib_lock);
485 + len = priv->dev.ports * num_mibs * sizeof(*priv->mib_stats);
486 + memset(priv->mib_stats, 0, len);
487 + ret = ar40xx_mib_flush(priv);
489 + mutex_unlock(&priv->mib_lock);
494 +ar40xx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
495 + struct switch_val *val)
497 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
499 + priv->vlan = !!val->value.i;
504 +ar40xx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
505 + struct switch_val *val)
507 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
509 + val->value.i = priv->vlan;
514 +ar40xx_sw_set_mirror_rx_enable(struct switch_dev *dev,
515 + const struct switch_attr *attr,
516 + struct switch_val *val)
518 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
520 + mutex_lock(&priv->reg_mutex);
521 + priv->mirror_rx = !!val->value.i;
522 + ar40xx_set_mirror_regs(priv);
523 + mutex_unlock(&priv->reg_mutex);
529 +ar40xx_sw_get_mirror_rx_enable(struct switch_dev *dev,
530 + const struct switch_attr *attr,
531 + struct switch_val *val)
533 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
535 + mutex_lock(&priv->reg_mutex);
536 + val->value.i = priv->mirror_rx;
537 + mutex_unlock(&priv->reg_mutex);
542 +ar40xx_sw_set_mirror_tx_enable(struct switch_dev *dev,
543 + const struct switch_attr *attr,
544 + struct switch_val *val)
546 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
548 + mutex_lock(&priv->reg_mutex);
549 + priv->mirror_tx = !!val->value.i;
550 + ar40xx_set_mirror_regs(priv);
551 + mutex_unlock(&priv->reg_mutex);
557 +ar40xx_sw_get_mirror_tx_enable(struct switch_dev *dev,
558 + const struct switch_attr *attr,
559 + struct switch_val *val)
561 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
563 + mutex_lock(&priv->reg_mutex);
564 + val->value.i = priv->mirror_tx;
565 + mutex_unlock(&priv->reg_mutex);
570 +ar40xx_sw_set_mirror_monitor_port(struct switch_dev *dev,
571 + const struct switch_attr *attr,
572 + struct switch_val *val)
574 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
576 + mutex_lock(&priv->reg_mutex);
577 + priv->monitor_port = val->value.i;
578 + ar40xx_set_mirror_regs(priv);
579 + mutex_unlock(&priv->reg_mutex);
585 +ar40xx_sw_get_mirror_monitor_port(struct switch_dev *dev,
586 + const struct switch_attr *attr,
587 + struct switch_val *val)
589 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
591 + mutex_lock(&priv->reg_mutex);
592 + val->value.i = priv->monitor_port;
593 + mutex_unlock(&priv->reg_mutex);
598 +ar40xx_sw_set_mirror_source_port(struct switch_dev *dev,
599 + const struct switch_attr *attr,
600 + struct switch_val *val)
602 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
604 + mutex_lock(&priv->reg_mutex);
605 + priv->source_port = val->value.i;
606 + ar40xx_set_mirror_regs(priv);
607 + mutex_unlock(&priv->reg_mutex);
613 +ar40xx_sw_get_mirror_source_port(struct switch_dev *dev,
614 + const struct switch_attr *attr,
615 + struct switch_val *val)
617 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
619 + mutex_lock(&priv->reg_mutex);
620 + val->value.i = priv->source_port;
621 + mutex_unlock(&priv->reg_mutex);
626 +ar40xx_sw_set_linkdown(struct switch_dev *dev,
627 + const struct switch_attr *attr,
628 + struct switch_val *val)
630 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
632 + if (val->value.i == 1)
633 + ar40xx_port_phy_linkdown(priv);
635 + ar40xx_phy_init(priv);
641 +ar40xx_sw_set_port_reset_mib(struct switch_dev *dev,
642 + const struct switch_attr *attr,
643 + struct switch_val *val)
645 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
649 + port = val->port_vlan;
650 + if (port >= dev->ports)
653 + mutex_lock(&priv->mib_lock);
654 + ret = ar40xx_mib_capture(priv);
658 + ar40xx_mib_fetch_port_stat(priv, port, true);
661 + mutex_unlock(&priv->mib_lock);
666 +ar40xx_sw_get_port_mib(struct switch_dev *dev,
667 + const struct switch_attr *attr,
668 + struct switch_val *val)
670 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
674 + char *buf = priv->buf;
676 + u32 num_mibs = ARRAY_SIZE(ar40xx_mibs);
678 + port = val->port_vlan;
679 + if (port >= dev->ports)
682 + mutex_lock(&priv->mib_lock);
683 + ret = ar40xx_mib_capture(priv);
687 + ar40xx_mib_fetch_port_stat(priv, port, false);
689 + len += snprintf(buf + len, sizeof(priv->buf) - len,
690 + "Port %d MIB counters\n",
693 + mib_stats = &priv->mib_stats[port * num_mibs];
694 + for (i = 0; i < num_mibs; i++)
695 + len += snprintf(buf + len, sizeof(priv->buf) - len,
697 + ar40xx_mibs[i].name,
700 + val->value.s = buf;
704 + mutex_unlock(&priv->mib_lock);
709 +ar40xx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
710 + struct switch_val *val)
712 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
714 + priv->vlan_id[val->port_vlan] = val->value.i;
719 +ar40xx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
720 + struct switch_val *val)
722 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
724 + val->value.i = priv->vlan_id[val->port_vlan];
729 +ar40xx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
731 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
732 + *vlan = priv->pvid[port];
737 +ar40xx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
739 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
741 + /* make sure no invalid PVIDs get set */
742 + if (vlan >= dev->vlans)
745 + priv->pvid[port] = vlan;
750 +ar40xx_read_port_link(struct ar40xx_priv *priv, int port,
751 + struct switch_port_link *link)
756 + memset(link, 0, sizeof(*link));
758 + status = ar40xx_read(priv, AR40XX_REG_PORT_STATUS(port));
760 + link->aneg = !!(status & AR40XX_PORT_AUTO_LINK_EN);
761 + if (link->aneg || (port != AR40XX_PORT_CPU))
762 + link->link = !!(status & AR40XX_PORT_STATUS_LINK_UP);
769 + link->duplex = !!(status & AR40XX_PORT_DUPLEX);
770 + link->tx_flow = !!(status & AR40XX_PORT_STATUS_TXFLOW);
771 + link->rx_flow = !!(status & AR40XX_PORT_STATUS_RXFLOW);
773 + speed = (status & AR40XX_PORT_SPEED) >>
774 + AR40XX_PORT_STATUS_SPEED_S;
777 + case AR40XX_PORT_SPEED_10M:
778 + link->speed = SWITCH_PORT_SPEED_10;
780 + case AR40XX_PORT_SPEED_100M:
781 + link->speed = SWITCH_PORT_SPEED_100;
783 + case AR40XX_PORT_SPEED_1000M:
784 + link->speed = SWITCH_PORT_SPEED_1000;
787 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
793 +ar40xx_sw_get_port_link(struct switch_dev *dev, int port,
794 + struct switch_port_link *link)
796 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
798 + ar40xx_read_port_link(priv, port, link);
802 +static const struct switch_attr ar40xx_sw_attr_globals[] = {
804 + .type = SWITCH_TYPE_INT,
805 + .name = "enable_vlan",
806 + .description = "Enable VLAN mode",
807 + .set = ar40xx_sw_set_vlan,
808 + .get = ar40xx_sw_get_vlan,
812 + .type = SWITCH_TYPE_NOVAL,
813 + .name = "reset_mibs",
814 + .description = "Reset all MIB counters",
815 + .set = ar40xx_sw_set_reset_mibs,
818 + .type = SWITCH_TYPE_INT,
819 + .name = "enable_mirror_rx",
820 + .description = "Enable mirroring of RX packets",
821 + .set = ar40xx_sw_set_mirror_rx_enable,
822 + .get = ar40xx_sw_get_mirror_rx_enable,
826 + .type = SWITCH_TYPE_INT,
827 + .name = "enable_mirror_tx",
828 + .description = "Enable mirroring of TX packets",
829 + .set = ar40xx_sw_set_mirror_tx_enable,
830 + .get = ar40xx_sw_get_mirror_tx_enable,
834 + .type = SWITCH_TYPE_INT,
835 + .name = "mirror_monitor_port",
836 + .description = "Mirror monitor port",
837 + .set = ar40xx_sw_set_mirror_monitor_port,
838 + .get = ar40xx_sw_get_mirror_monitor_port,
839 + .max = AR40XX_NUM_PORTS - 1
842 + .type = SWITCH_TYPE_INT,
843 + .name = "mirror_source_port",
844 + .description = "Mirror source port",
845 + .set = ar40xx_sw_set_mirror_source_port,
846 + .get = ar40xx_sw_get_mirror_source_port,
847 + .max = AR40XX_NUM_PORTS - 1
850 + .type = SWITCH_TYPE_INT,
851 + .name = "linkdown",
852 + .description = "Link down all the PHYs",
853 + .set = ar40xx_sw_set_linkdown,
858 +static const struct switch_attr ar40xx_sw_attr_port[] = {
860 + .type = SWITCH_TYPE_NOVAL,
861 + .name = "reset_mib",
862 + .description = "Reset single port MIB counters",
863 + .set = ar40xx_sw_set_port_reset_mib,
866 + .type = SWITCH_TYPE_STRING,
868 + .description = "Get port's MIB counters",
870 + .get = ar40xx_sw_get_port_mib,
874 +const struct switch_attr ar40xx_sw_attr_vlan[] = {
876 + .type = SWITCH_TYPE_INT,
878 + .description = "VLAN ID (0-4094)",
879 + .set = ar40xx_sw_set_vid,
880 + .get = ar40xx_sw_get_vid,
885 +/* End of swconfig support */
888 +ar40xx_wait_bit(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)
894 + t = ar40xx_read(priv, reg);
895 + if ((t & mask) == val)
898 + if (timeout-- <= 0)
901 + usleep_range(10, 20);
904 + pr_err("ar40xx: timeout for reg %08x: %08x & %08x != %08x\n",
905 + (unsigned int)reg, t, mask, val);
910 +ar40xx_atu_flush(struct ar40xx_priv *priv)
914 + ret = ar40xx_wait_bit(priv, AR40XX_REG_ATU_FUNC,
915 + AR40XX_ATU_FUNC_BUSY, 0);
917 + ar40xx_write(priv, AR40XX_REG_ATU_FUNC,
918 + AR40XX_ATU_FUNC_OP_FLUSH |
919 + AR40XX_ATU_FUNC_BUSY);
925 +ar40xx_ess_reset(struct ar40xx_priv *priv)
927 + reset_control_assert(priv->ess_rst);
929 + reset_control_deassert(priv->ess_rst);
930 + /* Waiting for all inner tables init done.
935 + pr_info("ESS reset ok!\n");
938 +/* Start of psgmii self test */
941 +ar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv)
944 + struct mii_bus *bus = priv->mii_bus;
945 + /* reset phy psgmii */
946 + /* fix phy psgmii RX 20bit */
947 + mdiobus_write(bus, 5, 0x0, 0x005b);
948 + /* reset phy psgmii */
949 + mdiobus_write(bus, 5, 0x0, 0x001b);
950 + /* release reset phy psgmii */
951 + mdiobus_write(bus, 5, 0x0, 0x005b);
953 + for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
956 + status = ar40xx_phy_mmd_read(priv, 5, 1, 0x28);
957 + if (status & BIT(0))
959 + /* Polling interval to check PSGMII PLL in malibu is ready
960 + * the worst time is 8.67ms
961 + * for 25MHz reference clock
962 + * [512+(128+2048)*49]*80ns+100us
967 + /*check malibu psgmii calibration done end..*/
969 + /*freeze phy psgmii RX CDR*/
970 + mdiobus_write(bus, 5, 0x1a, 0x2230);
972 + ar40xx_ess_reset(priv);
974 + /*check psgmii calibration done start*/
975 + for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
978 + status = ar40xx_psgmii_read(priv, 0xa0);
979 + if (status & BIT(0))
981 + /* Polling interval to check PSGMII PLL in ESS is ready */
985 + /* check dakota psgmii calibration done end..*/
987 + /* relesae phy psgmii RX CDR */
988 + mdiobus_write(bus, 5, 0x1a, 0x3230);
989 + /* release phy psgmii RX 20bit */
990 + mdiobus_write(bus, 5, 0x0, 0x005f);
994 +ar40xx_psgmii_single_phy_testing(struct ar40xx_priv *priv, int phy)
997 + u32 tx_ok, tx_error;
998 + u32 rx_ok, rx_error;
1001 + u32 tx_all_ok, rx_all_ok;
1002 + struct mii_bus *bus = priv->mii_bus;
1004 + mdiobus_write(bus, phy, 0x0, 0x9000);
1005 + mdiobus_write(bus, phy, 0x0, 0x4140);
1007 + for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
1010 + status = mdiobus_read(bus, phy, 0x11);
1011 + if (status & AR40XX_PHY_SPEC_STATUS_LINK)
1013 + /* the polling interval to check if the PHY link up or not
1014 + * maxwait_timer: 750 ms +/-10 ms
1015 + * minwait_timer : 1 us +/- 0.1us
1016 + * time resides in minwait_timer ~ maxwait_timer
1017 + * see IEEE 802.3 section 40.4.5.2
1022 + /* enable check */
1023 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000);
1024 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003);
1026 + /* start traffic */
1027 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000);
1028 + /* wait for all traffic end
1029 + * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
1033 + /* check counter */
1034 + tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
1035 + tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
1036 + tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
1037 + rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
1038 + rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
1039 + rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
1040 + tx_all_ok = tx_ok + (tx_ok_high16 << 16);
1041 + rx_all_ok = rx_ok + (rx_ok_high16 << 16);
1042 + if (tx_all_ok == 0x1000 && tx_error == 0) {
1044 + priv->phy_t_status &= (~BIT(phy));
1046 + pr_info("PHY %d single test PSGMII issue happen!\n", phy);
1047 + priv->phy_t_status |= BIT(phy);
1050 + mdiobus_write(bus, phy, 0x0, 0x1840);
1054 +ar40xx_psgmii_all_phy_testing(struct ar40xx_priv *priv)
1057 + struct mii_bus *bus = priv->mii_bus;
1059 + mdiobus_write(bus, 0x1f, 0x0, 0x9000);
1060 + mdiobus_write(bus, 0x1f, 0x0, 0x4140);
1062 + for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
1063 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1066 + status = mdiobus_read(bus, phy, 0x11);
1067 + if (!(status & BIT(10)))
1071 + if (phy >= (AR40XX_NUM_PORTS - 1))
1073 + /* The polling interva to check if the PHY link up or not */
1076 + /* enable check */
1077 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000);
1078 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003);
1080 + /* start traffic */
1081 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000);
1082 + /* wait for all traffic end
1083 + * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
1087 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1088 + u32 tx_ok, tx_error;
1089 + u32 rx_ok, rx_error;
1092 + u32 tx_all_ok, rx_all_ok;
1094 + /* check counter */
1095 + tx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);
1096 + tx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);
1097 + tx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);
1098 + rx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);
1099 + rx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);
1100 + rx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);
1101 + tx_all_ok = tx_ok + (tx_ok_high16<<16);
1102 + rx_all_ok = rx_ok + (rx_ok_high16<<16);
1103 + if (tx_all_ok == 0x1000 && tx_error == 0) {
1105 + priv->phy_t_status &= ~BIT(phy + 8);
1107 + pr_info("PHY%d test see issue!\n", phy);
1108 + priv->phy_t_status |= BIT(phy + 8);
1112 + pr_debug("PHY all test 0x%x \r\n", priv->phy_t_status);
1116 +ar40xx_psgmii_self_test(struct ar40xx_priv *priv)
1119 + struct mii_bus *bus = priv->mii_bus;
1121 + ar40xx_malibu_psgmii_ess_reset(priv);
1123 + /* switch to access MII reg for copper */
1124 + mdiobus_write(bus, 4, 0x1f, 0x8500);
1125 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1126 + /*enable phy mdio broadcast write*/
1127 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f);
1129 + /* force no link by power down */
1130 + mdiobus_write(bus, 0x1f, 0x0, 0x1840);
1132 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000);
1133 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0);
1135 + /*fix mdi status */
1136 + mdiobus_write(bus, 0x1f, 0x10, 0x6800);
1137 + for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
1138 + priv->phy_t_status = 0;
1140 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1141 + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
1142 + AR40XX_PORT_LOOKUP_LOOPBACK,
1143 + AR40XX_PORT_LOOKUP_LOOPBACK);
1146 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)
1147 + ar40xx_psgmii_single_phy_testing(priv, phy);
1149 + ar40xx_psgmii_all_phy_testing(priv);
1151 + if (priv->phy_t_status)
1152 + ar40xx_malibu_psgmii_ess_reset(priv);
1157 + if (i >= AR40XX_PSGMII_CALB_NUM)
1158 + pr_info("PSGMII cannot recover\n");
1160 + pr_debug("PSGMII recovered after %d times reset\n", i);
1162 + /* configuration recover */
1163 + /* packet number */
1164 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0);
1165 + /* disable check */
1166 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0);
1167 + /* disable traffic */
1168 + ar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0);
1172 +ar40xx_psgmii_self_test_clean(struct ar40xx_priv *priv)
1175 + struct mii_bus *bus = priv->mii_bus;
1177 + /* disable phy internal loopback */
1178 + mdiobus_write(bus, 0x1f, 0x10, 0x6860);
1179 + mdiobus_write(bus, 0x1f, 0x0, 0x9040);
1181 + for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1182 + /* disable mac loop back */
1183 + ar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
1184 + AR40XX_PORT_LOOKUP_LOOPBACK, 0);
1185 + /* disable phy mdio broadcast write */
1186 + ar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f);
1189 + /* clear fdb entry */
1190 + ar40xx_atu_flush(priv);
1193 +/* End of psgmii self test */
1196 +ar40xx_mac_mode_init(struct ar40xx_priv *priv, u32 mode)
1198 + if (mode == PORT_WRAPPER_PSGMII) {
1199 + ar40xx_psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200);
1200 + ar40xx_psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380);
1205 +int ar40xx_cpuport_setup(struct ar40xx_priv *priv)
1209 + t = AR40XX_PORT_STATUS_TXFLOW |
1210 + AR40XX_PORT_STATUS_RXFLOW |
1211 + AR40XX_PORT_TXHALF_FLOW |
1212 + AR40XX_PORT_DUPLEX |
1213 + AR40XX_PORT_SPEED_1000M;
1214 + ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
1215 + usleep_range(10, 20);
1217 + t |= AR40XX_PORT_TX_EN |
1218 + AR40XX_PORT_RX_EN;
1219 + ar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);
1225 +ar40xx_init_port(struct ar40xx_priv *priv, int port)
1229 + ar40xx_rmw(priv, AR40XX_REG_PORT_STATUS(port),
1230 + AR40XX_PORT_AUTO_LINK_EN, 0);
1232 + ar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);
1234 + ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);
1236 + t = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH << AR40XX_PORT_VLAN1_OUT_MODE_S;
1237 + ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
1239 + t = AR40XX_PORT_LOOKUP_LEARN;
1240 + t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
1241 + ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
1245 +ar40xx_init_globals(struct ar40xx_priv *priv)
1249 + /* enable CPU port and disable mirror port */
1250 + t = AR40XX_FWD_CTRL0_CPU_PORT_EN |
1251 + AR40XX_FWD_CTRL0_MIRROR_PORT;
1252 + ar40xx_write(priv, AR40XX_REG_FWD_CTRL0, t);
1254 + /* forward multicast and broadcast frames to CPU */
1255 + t = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S) |
1256 + (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S) |
1257 + (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S);
1258 + ar40xx_write(priv, AR40XX_REG_FWD_CTRL1, t);
1260 + /* enable jumbo frames */
1261 + ar40xx_rmw(priv, AR40XX_REG_MAX_FRAME_SIZE,
1262 + AR40XX_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1264 + /* Enable MIB counters */
1265 + ar40xx_rmw(priv, AR40XX_REG_MODULE_EN, 0,
1266 + AR40XX_MODULE_EN_MIB);
1269 + ar40xx_write(priv, AR40XX_REG_EEE_CTRL, 0);
1271 + /* set flowctrl thershold for cpu port */
1272 + t = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |
1273 + AR40XX_PORT0_FC_THRESH_OFF_DFLT;
1274 + ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
1278 +ar40xx_malibu_init(struct ar40xx_priv *priv)
1281 + struct mii_bus *bus;
1284 + bus = priv->mii_bus;
1286 + /* war to enable AZ transmitting ability */
1287 + ar40xx_phy_mmd_write(priv, AR40XX_PSGMII_ID, 1,
1288 + AR40XX_MALIBU_PSGMII_MODE_CTRL,
1289 + AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL);
1290 + for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
1291 + /* change malibu control_dac */
1292 + val = ar40xx_phy_mmd_read(priv, i, 7,
1293 + AR40XX_MALIBU_PHY_MMD7_DAC_CTRL);
1294 + val &= ~AR40XX_MALIBU_DAC_CTRL_MASK;
1295 + val |= AR40XX_MALIBU_DAC_CTRL_VALUE;
1296 + ar40xx_phy_mmd_write(priv, i, 7,
1297 + AR40XX_MALIBU_PHY_MMD7_DAC_CTRL, val);
1298 + if (i == AR40XX_MALIBU_PHY_LAST_ADDR) {
1299 + /* to avoid goes into hibernation */
1300 + val = ar40xx_phy_mmd_read(priv, i, 3,
1301 + AR40XX_MALIBU_PHY_RLP_CTRL);
1303 + ar40xx_phy_mmd_write(priv, i, 3,
1304 + AR40XX_MALIBU_PHY_RLP_CTRL, val);
1308 + /* adjust psgmii serdes tx amp */
1309 + mdiobus_write(bus, AR40XX_PSGMII_ID, AR40XX_PSGMII_TX_DRIVER_1_CTRL,
1310 + AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
1314 +ar40xx_hw_init(struct ar40xx_priv *priv)
1318 + ar40xx_ess_reset(priv);
1320 + if (priv->mii_bus)
1321 + ar40xx_malibu_init(priv);
1325 + ar40xx_psgmii_self_test(priv);
1326 + ar40xx_psgmii_self_test_clean(priv);
1328 + ar40xx_mac_mode_init(priv, priv->mac_mode);
1330 + for (i = 0; i < priv->dev.ports; i++)
1331 + ar40xx_init_port(priv, i);
1333 + ar40xx_init_globals(priv);
1338 +/* Start of qm error WAR */
1341 +int ar40xx_force_1g_full(struct ar40xx_priv *priv, u32 port_id)
1345 + if (port_id < 0 || port_id > 6)
1348 + reg = AR40XX_REG_PORT_STATUS(port_id);
1349 + return ar40xx_rmw(priv, reg, AR40XX_PORT_SPEED,
1350 + (AR40XX_PORT_SPEED_1000M | AR40XX_PORT_DUPLEX));
1354 +int ar40xx_get_qm_status(struct ar40xx_priv *priv,
1355 + u32 port_id, u32 *qm_buffer_err)
1360 + if (port_id < 1 || port_id > 5) {
1361 + *qm_buffer_err = 0;
1365 + if (port_id < 4) {
1366 + reg = AR40XX_REG_QM_PORT0_3_QNUM;
1367 + ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
1368 + qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
1369 + /* every 8 bits for each port */
1370 + *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;
1372 + reg = AR40XX_REG_QM_PORT4_6_QNUM;
1373 + ar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
1374 + qm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
1375 + /* every 8 bits for each port */
1376 + *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;
1383 +ar40xx_sw_mac_polling_task(struct ar40xx_priv *priv)
1385 + static int task_count;
1388 + u32 link, speed, duplex;
1389 + u32 qm_buffer_err;
1390 + u16 port_phy_status[AR40XX_NUM_PORTS];
1391 + static u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
1392 + static u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
1393 + struct mii_bus *bus = NULL;
1395 + if (!priv || !priv->mii_bus)
1398 + bus = priv->mii_bus;
1402 + for (i = 1; i < AR40XX_NUM_PORTS; ++i) {
1403 + port_phy_status[i] =
1404 + mdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS);
1405 + speed = link = duplex = port_phy_status[i];
1406 + speed &= AR40XX_PHY_SPEC_STATUS_SPEED;
1408 + link &= AR40XX_PHY_SPEC_STATUS_LINK;
1410 + duplex &= AR40XX_PHY_SPEC_STATUS_DUPLEX;
1413 + if (link != priv->ar40xx_port_old_link[i]) {
1416 + if ((priv->ar40xx_port_old_link[i] ==
1417 + AR40XX_PORT_LINK_UP) &&
1418 + (link == AR40XX_PORT_LINK_DOWN)) {
1419 + /* LINK_EN disable(MAC force mode)*/
1420 + reg = AR40XX_REG_PORT_STATUS(i);
1421 + ar40xx_rmw(priv, reg,
1422 + AR40XX_PORT_AUTO_LINK_EN, 0);
1424 + /* Check queue buffer */
1425 + qm_err_cnt[i] = 0;
1426 + ar40xx_get_qm_status(priv, i, &qm_buffer_err);
1427 + if (qm_buffer_err) {
1428 + priv->ar40xx_port_qm_buf[i] =
1429 + AR40XX_QM_NOT_EMPTY;
1433 + priv->ar40xx_port_qm_buf[i] =
1435 + ar40xx_force_1g_full(priv, i);
1436 + /* Ref:QCA8337 Datasheet,Clearing
1437 + * MENU_CTRL_EN prevents phy to
1438 + * stuck in 100BT mode when
1439 + * bringing up the link
1441 + ar40xx_phy_dbg_read(priv, i-1,
1442 + AR40XX_PHY_DEBUG_0,
1444 + phy_val &= (~AR40XX_PHY_MANU_CTRL_EN);
1445 + ar40xx_phy_dbg_write(priv, i-1,
1446 + AR40XX_PHY_DEBUG_0,
1449 + priv->ar40xx_port_old_link[i] = link;
1450 + } else if ((priv->ar40xx_port_old_link[i] ==
1451 + AR40XX_PORT_LINK_DOWN) &&
1452 + (link == AR40XX_PORT_LINK_UP)) {
1454 + if (priv->port_link_up[i] < 1) {
1455 + ++priv->port_link_up[i];
1457 + /* Change port status */
1458 + reg = AR40XX_REG_PORT_STATUS(i);
1459 + value = ar40xx_read(priv, reg);
1460 + priv->port_link_up[i] = 0;
1462 + value &= ~(AR40XX_PORT_DUPLEX |
1463 + AR40XX_PORT_SPEED);
1464 + value |= speed | (duplex ? BIT(6) : 0);
1465 + ar40xx_write(priv, reg, value);
1466 + /* clock switch need such time
1469 + usleep_range(100, 200);
1471 + value |= AR40XX_PORT_AUTO_LINK_EN;
1472 + ar40xx_write(priv, reg, value);
1473 + /* HW need such time to make sure link
1474 + * stable before enable MAC
1476 + usleep_range(100, 200);
1478 + if (speed == AR40XX_PORT_SPEED_100M) {
1480 + /* Enable @100M, if down to 10M
1481 + * clock will change smoothly
1483 + ar40xx_phy_dbg_read(priv, i-1,
1487 + AR40XX_PHY_MANU_CTRL_EN;
1488 + ar40xx_phy_dbg_write(priv, i-1,
1492 + priv->ar40xx_port_old_link[i] = link;
1497 + if (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) {
1499 + ar40xx_get_qm_status(priv, i, &qm_buffer_err);
1500 + if (qm_buffer_err) {
1503 + priv->ar40xx_port_qm_buf[i] =
1505 + qm_err_cnt[i] = 0;
1506 + ar40xx_force_1g_full(priv, i);
1513 +ar40xx_qm_err_check_work_task(struct work_struct *work)
1515 + struct ar40xx_priv *priv = container_of(work, struct ar40xx_priv,
1518 + mutex_lock(&priv->qm_lock);
1520 + ar40xx_sw_mac_polling_task(priv);
1522 + mutex_unlock(&priv->qm_lock);
1524 + schedule_delayed_work(&priv->qm_dwork,
1525 + msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
1529 +ar40xx_qm_err_check_work_start(struct ar40xx_priv *priv)
1531 + mutex_init(&priv->qm_lock);
1533 + INIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task);
1535 + schedule_delayed_work(&priv->qm_dwork,
1536 + msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
1541 +/* End of qm error WAR */
1544 +ar40xx_vlan_init(struct ar40xx_priv *priv)
1547 + unsigned long bmp;
1549 + /* By default Enable VLAN */
1551 + priv->vlan_table[AR40XX_LAN_VLAN] = priv->cpu_bmp | priv->lan_bmp;
1552 + priv->vlan_table[AR40XX_WAN_VLAN] = priv->cpu_bmp | priv->wan_bmp;
1553 + priv->vlan_tagged = priv->cpu_bmp;
1554 + bmp = priv->lan_bmp;
1555 + for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
1556 + priv->pvid[port] = AR40XX_LAN_VLAN;
1558 + bmp = priv->wan_bmp;
1559 + for_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)
1560 + priv->pvid[port] = AR40XX_WAN_VLAN;
1566 +ar40xx_mib_work_func(struct work_struct *work)
1568 + struct ar40xx_priv *priv;
1571 + priv = container_of(work, struct ar40xx_priv, mib_work.work);
1573 + mutex_lock(&priv->mib_lock);
1575 + err = ar40xx_mib_capture(priv);
1579 + ar40xx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1582 + priv->mib_next_port++;
1583 + if (priv->mib_next_port >= priv->dev.ports)
1584 + priv->mib_next_port = 0;
1586 + mutex_unlock(&priv->mib_lock);
1588 + schedule_delayed_work(&priv->mib_work,
1589 + msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
1593 +ar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members)
1596 + u32 egress, ingress;
1597 + u32 pvid = priv->vlan_id[priv->pvid[port]];
1600 + egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
1601 + ingress = AR40XX_IN_SECURE;
1603 + egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
1604 + ingress = AR40XX_IN_PORT_ONLY;
1607 + t = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;
1608 + t |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
1609 + ar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);
1611 + t = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
1612 + t |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
1613 + ar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);
1616 + t |= AR40XX_PORT_LOOKUP_LEARN;
1617 + t |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;
1618 + t |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
1619 + ar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);
1623 +ar40xx_vtu_op(struct ar40xx_priv *priv, u32 op, u32 val)
1625 + if (ar40xx_wait_bit(priv, AR40XX_REG_VTU_FUNC1,
1626 + AR40XX_VTU_FUNC1_BUSY, 0))
1629 + if ((op & AR40XX_VTU_FUNC1_OP) == AR40XX_VTU_FUNC1_OP_LOAD)
1630 + ar40xx_write(priv, AR40XX_REG_VTU_FUNC0, val);
1632 + op |= AR40XX_VTU_FUNC1_BUSY;
1633 + ar40xx_write(priv, AR40XX_REG_VTU_FUNC1, op);
1637 +ar40xx_vtu_load_vlan(struct ar40xx_priv *priv, u32 vid, u32 port_mask)
1643 + op = AR40XX_VTU_FUNC1_OP_LOAD | (vid << AR40XX_VTU_FUNC1_VID_S);
1644 + val = AR40XX_VTU_FUNC0_VALID | AR40XX_VTU_FUNC0_IVL;
1645 + for (i = 0; i < AR40XX_NUM_PORTS; i++) {
1648 + if ((port_mask & BIT(i)) == 0)
1649 + mode = AR40XX_VTU_FUNC0_EG_MODE_NOT;
1650 + else if (priv->vlan == 0)
1651 + mode = AR40XX_VTU_FUNC0_EG_MODE_KEEP;
1652 + else if ((priv->vlan_tagged & BIT(i)) ||
1653 + (priv->vlan_id[priv->pvid[i]] != vid))
1654 + mode = AR40XX_VTU_FUNC0_EG_MODE_TAG;
1656 + mode = AR40XX_VTU_FUNC0_EG_MODE_UNTAG;
1658 + val |= mode << AR40XX_VTU_FUNC0_EG_MODE_S(i);
1660 + ar40xx_vtu_op(priv, op, val);
1664 +ar40xx_vtu_flush(struct ar40xx_priv *priv)
1666 + ar40xx_vtu_op(priv, AR40XX_VTU_FUNC1_OP_FLUSH, 0);
1670 +ar40xx_sw_hw_apply(struct switch_dev *dev)
1672 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
1673 + u8 portmask[AR40XX_NUM_PORTS];
1676 + mutex_lock(&priv->reg_mutex);
1677 + /* flush all vlan entries */
1678 + ar40xx_vtu_flush(priv);
1680 + memset(portmask, 0, sizeof(portmask));
1682 + for (j = 0; j < AR40XX_MAX_VLANS; j++) {
1683 + u8 vp = priv->vlan_table[j];
1688 + for (i = 0; i < dev->ports; i++) {
1692 + portmask[i] |= vp & ~mask;
1695 + ar40xx_vtu_load_vlan(priv, priv->vlan_id[j],
1696 + priv->vlan_table[j]);
1699 + /* 8021q vlan disabled */
1700 + for (i = 0; i < dev->ports; i++) {
1701 + if (i == AR40XX_PORT_CPU)
1704 + portmask[i] = BIT(AR40XX_PORT_CPU);
1705 + portmask[AR40XX_PORT_CPU] |= BIT(i);
1709 + /* update the port destination mask registers and tag settings */
1710 + for (i = 0; i < dev->ports; i++)
1711 + ar40xx_setup_port(priv, i, portmask[i]);
1713 + ar40xx_set_mirror_regs(priv);
1715 + mutex_unlock(&priv->reg_mutex);
1720 +ar40xx_sw_reset_switch(struct switch_dev *dev)
1722 + struct ar40xx_priv *priv = swdev_to_ar40xx(dev);
1725 + mutex_lock(&priv->reg_mutex);
1726 + memset(&priv->vlan, 0, sizeof(struct ar40xx_priv) -
1727 + offsetof(struct ar40xx_priv, vlan));
1729 + for (i = 0; i < AR40XX_MAX_VLANS; i++)
1730 + priv->vlan_id[i] = i;
1732 + ar40xx_vlan_init(priv);
1734 + priv->mirror_rx = false;
1735 + priv->mirror_tx = false;
1736 + priv->source_port = 0;
1737 + priv->monitor_port = 0;
1739 + mutex_unlock(&priv->reg_mutex);
1741 + rv = ar40xx_sw_hw_apply(dev);
1746 +ar40xx_start(struct ar40xx_priv *priv)
1750 + ret = ar40xx_hw_init(priv);
1754 + ret = ar40xx_sw_reset_switch(&priv->dev);
1758 + /* at last, setup cpu port */
1759 + ret = ar40xx_cpuport_setup(priv);
1763 + schedule_delayed_work(&priv->mib_work,
1764 + msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));
1766 + ar40xx_qm_err_check_work_start(priv);
1771 +static const struct switch_dev_ops ar40xx_sw_ops = {
1773 + .attr = ar40xx_sw_attr_globals,
1774 + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_globals),
1777 + .attr = ar40xx_sw_attr_port,
1778 + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_port),
1781 + .attr = ar40xx_sw_attr_vlan,
1782 + .n_attr = ARRAY_SIZE(ar40xx_sw_attr_vlan),
1784 + .get_port_pvid = ar40xx_sw_get_pvid,
1785 + .set_port_pvid = ar40xx_sw_set_pvid,
1786 + .get_vlan_ports = ar40xx_sw_get_ports,
1787 + .set_vlan_ports = ar40xx_sw_set_ports,
1788 + .apply_config = ar40xx_sw_hw_apply,
1789 + .reset_switch = ar40xx_sw_reset_switch,
1790 + .get_port_link = ar40xx_sw_get_port_link,
1793 +/* Start of phy driver support */
1795 +static const u32 ar40xx_phy_ids[] = {
1797 + 0x004dd0b2, /* AR40xx */
1801 +ar40xx_phy_match(u32 phy_id)
1805 + for (i = 0; i < ARRAY_SIZE(ar40xx_phy_ids); i++)
1806 + if (phy_id == ar40xx_phy_ids[i])
1813 +is_ar40xx_phy(struct mii_bus *bus)
1817 + for (i = 0; i < 4; i++) {
1820 + phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1821 + phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1822 + if (!ar40xx_phy_match(phy_id))
1830 +ar40xx_phy_probe(struct phy_device *phydev)
1832 + if (!is_ar40xx_phy(phydev->mdio.bus))
1835 + ar40xx_priv->mii_bus = phydev->mdio.bus;
1836 + phydev->priv = ar40xx_priv;
1837 + if (phydev->mdio.addr == 0)
1838 + ar40xx_priv->phy = phydev;
1840 + phydev->supported |= SUPPORTED_1000baseT_Full;
1841 + phydev->advertising |= ADVERTISED_1000baseT_Full;
1846 +ar40xx_phy_remove(struct phy_device *phydev)
1848 + ar40xx_priv->mii_bus = NULL;
1849 + phydev->priv = NULL;
1853 +ar40xx_phy_config_init(struct phy_device *phydev)
1859 +ar40xx_phy_read_status(struct phy_device *phydev)
1861 + if (phydev->mdio.addr != 0)
1862 + return genphy_read_status(phydev);
1868 +ar40xx_phy_config_aneg(struct phy_device *phydev)
1870 + if (phydev->mdio.addr == 0)
1873 + return genphy_config_aneg(phydev);
1876 +static struct phy_driver ar40xx_phy_driver = {
1877 + .phy_id = 0x004d0000,
1878 + .name = "QCA Malibu",
1879 + .phy_id_mask = 0xffff0000,
1880 + .features = PHY_BASIC_FEATURES,
1881 + .probe = ar40xx_phy_probe,
1882 + .remove = ar40xx_phy_remove,
1883 + .config_init = ar40xx_phy_config_init,
1884 + .config_aneg = ar40xx_phy_config_aneg,
1885 + .read_status = ar40xx_phy_read_status,
1888 +static uint16_t ar40xx_gpio_get_phy(unsigned int offset)
1890 + return offset / 4;
1893 +static uint16_t ar40xx_gpio_get_reg(unsigned int offset)
1895 + return 0x8074 + offset % 4;
1898 +static void ar40xx_gpio_set(struct gpio_chip *gc, unsigned int offset,
1901 + struct ar40xx_priv *priv = gpiochip_get_data(gc);
1903 + ar40xx_phy_mmd_write(priv, ar40xx_gpio_get_phy(offset), 0x7,
1904 + ar40xx_gpio_get_reg(offset),
1905 + value ? 0xA000 : 0x8000);
1908 +static int ar40xx_gpio_get(struct gpio_chip *gc, unsigned offset)
1910 + struct ar40xx_priv *priv = gpiochip_get_data(gc);
1912 + return ar40xx_phy_mmd_read(priv, ar40xx_gpio_get_phy(offset), 0x7,
1913 + ar40xx_gpio_get_reg(offset)) == 0xA000;
1916 +static int ar40xx_gpio_get_dir(struct gpio_chip *gc, unsigned offset)
1918 + return 0; /* only out direction */
1921 +static int ar40xx_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
1925 + * the direction out value is used to set the initial value.
1926 + * support of this function is required by leds-gpio.c
1928 + ar40xx_gpio_set(gc, offset, value);
1932 +static void ar40xx_register_gpio(struct device *pdev,
1933 + struct ar40xx_priv *priv,
1934 + struct device_node *switch_node)
1936 + struct gpio_chip *gc;
1939 + gc = devm_kzalloc(pdev, sizeof(*gc), GFP_KERNEL);
1943 + gc->label = "ar40xx_gpio",
1945 + gc->ngpio = 5 /* mmd 0 - 4 */ * 4 /* 0x8074 - 0x8077 */,
1946 + gc->parent = pdev;
1947 + gc->owner = THIS_MODULE;
1949 + gc->get_direction = ar40xx_gpio_get_dir;
1950 + gc->direction_output = ar40xx_gpio_dir_out;
1951 + gc->get = ar40xx_gpio_get;
1952 + gc->set = ar40xx_gpio_set;
1953 + gc->can_sleep = true;
1954 + gc->label = priv->dev.name;
1955 + gc->of_node = switch_node;
1957 + err = devm_gpiochip_add_data(pdev, gc, priv);
1959 + dev_err(pdev, "Failed to register gpio %d.\n", err);
1962 +/* End of phy driver support */
1964 +/* Platform driver probe function */
1966 +static int ar40xx_probe(struct platform_device *pdev)
1968 + struct device_node *switch_node;
1969 + struct device_node *psgmii_node;
1970 + const __be32 *mac_mode;
1971 + struct clk *ess_clk;
1972 + struct switch_dev *swdev;
1973 + struct ar40xx_priv *priv;
1976 + struct resource psgmii_base = {0};
1977 + struct resource switch_base = {0};
1980 + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1984 + platform_set_drvdata(pdev, priv);
1985 + ar40xx_priv = priv;
1987 + switch_node = of_node_get(pdev->dev.of_node);
1988 + if (of_address_to_resource(switch_node, 0, &switch_base) != 0)
1991 + priv->hw_addr = devm_ioremap_resource(&pdev->dev, &switch_base);
1992 + if (IS_ERR(priv->hw_addr)) {
1993 + dev_err(&pdev->dev, "Failed to ioremap switch_base!\n");
1994 + return PTR_ERR(priv->hw_addr);
1997 + /*psgmii dts get*/
1998 + psgmii_node = of_find_node_by_name(NULL, "ess-psgmii");
1999 + if (!psgmii_node) {
2000 + dev_err(&pdev->dev, "Failed to find ess-psgmii node!\n");
2004 + if (of_address_to_resource(psgmii_node, 0, &psgmii_base) != 0)
2007 + priv->psgmii_hw_addr = devm_ioremap_resource(&pdev->dev, &psgmii_base);
2008 + if (IS_ERR(priv->psgmii_hw_addr)) {
2009 + dev_err(&pdev->dev, "psgmii ioremap fail!\n");
2010 + return PTR_ERR(priv->psgmii_hw_addr);
2013 + mac_mode = of_get_property(switch_node, "switch_mac_mode", &len);
2015 + dev_err(&pdev->dev, "Failed to read switch_mac_mode\n");
2018 + priv->mac_mode = be32_to_cpup(mac_mode);
2020 + ess_clk = of_clk_get_by_name(switch_node, "ess_clk");
2022 + clk_prepare_enable(ess_clk);
2024 + priv->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst");
2025 + if (IS_ERR(priv->ess_rst)) {
2026 + dev_err(&pdev->dev, "Failed to get ess_rst control!\n");
2027 + return PTR_ERR(priv->ess_rst);
2030 + if (of_property_read_u32(switch_node, "switch_cpu_bmp",
2031 + &priv->cpu_bmp) ||
2032 + of_property_read_u32(switch_node, "switch_lan_bmp",
2033 + &priv->lan_bmp) ||
2034 + of_property_read_u32(switch_node, "switch_wan_bmp",
2035 + &priv->wan_bmp)) {
2036 + dev_err(&pdev->dev, "Failed to read port properties\n");
2040 + ret = phy_driver_register(&ar40xx_phy_driver, THIS_MODULE);
2042 + dev_err(&pdev->dev, "Failed to register ar40xx phy driver!\n");
2046 + mutex_init(&priv->reg_mutex);
2047 + mutex_init(&priv->mib_lock);
2048 + INIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func);
2050 + /* register switch */
2051 + swdev = &priv->dev;
2053 + swdev->alias = dev_name(&priv->mii_bus->dev);
2055 + swdev->cpu_port = AR40XX_PORT_CPU;
2056 + swdev->name = "QCA AR40xx";
2057 + swdev->vlans = AR40XX_MAX_VLANS;
2058 + swdev->ports = AR40XX_NUM_PORTS;
2059 + swdev->ops = &ar40xx_sw_ops;
2060 + ret = register_switch(swdev, NULL);
2062 + goto err_unregister_phy;
2064 + num_mibs = ARRAY_SIZE(ar40xx_mibs);
2065 + len = priv->dev.ports * num_mibs *
2066 + sizeof(*priv->mib_stats);
2067 + priv->mib_stats = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
2068 + if (!priv->mib_stats) {
2070 + goto err_unregister_switch;
2073 + ar40xx_start(priv);
2075 + if (of_property_read_bool(switch_node, "gpio-controller"))
2076 + ar40xx_register_gpio(&pdev->dev, ar40xx_priv, switch_node);
2080 +err_unregister_switch:
2081 + unregister_switch(&priv->dev);
2082 +err_unregister_phy:
2083 + phy_driver_unregister(&ar40xx_phy_driver);
2084 + platform_set_drvdata(pdev, NULL);
2088 +static int ar40xx_remove(struct platform_device *pdev)
2090 + struct ar40xx_priv *priv = platform_get_drvdata(pdev);
2092 + cancel_delayed_work_sync(&priv->qm_dwork);
2093 + cancel_delayed_work_sync(&priv->mib_work);
2095 + unregister_switch(&priv->dev);
2097 + phy_driver_unregister(&ar40xx_phy_driver);
2102 +static const struct of_device_id ar40xx_of_mtable[] = {
2103 + {.compatible = "qcom,ess-switch" },
2107 +struct platform_driver ar40xx_drv = {
2108 + .probe = ar40xx_probe,
2109 + .remove = ar40xx_remove,
2112 + .of_match_table = ar40xx_of_mtable,
2116 +module_platform_driver(ar40xx_drv);
2118 +MODULE_DESCRIPTION("IPQ40XX ESS driver");
2119 +MODULE_LICENSE("Dual BSD/GPL");
2121 +++ b/drivers/net/phy/ar40xx.h
2124 + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
2126 + * Permission to use, copy, modify, and/or distribute this software for
2127 + * any purpose with or without fee is hereby granted, provided that the
2128 + * above copyright notice and this permission notice appear in all copies.
2129 + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
2130 + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
2131 + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
2132 + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
2133 + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
2134 + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
2135 + * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
2138 + #ifndef __AR40XX_H
2141 +#define AR40XX_MAX_VLANS 128
2142 +#define AR40XX_NUM_PORTS 6
2143 +#define AR40XX_NUM_PHYS 5
2145 +#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
2147 +struct ar40xx_priv {
2148 + struct switch_dev dev;
2150 + u8 __iomem *hw_addr;
2151 + u8 __iomem *psgmii_hw_addr;
2153 + struct reset_control *ess_rst;
2158 + struct mii_bus *mii_bus;
2159 + struct phy_device *phy;
2161 + /* mutex for qm task */
2162 + struct mutex qm_lock;
2163 + struct delayed_work qm_dwork;
2164 + u32 port_link_up[AR40XX_NUM_PORTS];
2165 + u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
2166 + u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
2170 + /* mutex for switch reg access */
2171 + struct mutex reg_mutex;
2173 + /* mutex for mib task */
2174 + struct mutex mib_lock;
2175 + struct delayed_work mib_work;
2176 + int mib_next_port;
2181 + /* all fields below will be cleared on reset */
2183 + u16 vlan_id[AR40XX_MAX_VLANS];
2184 + u8 vlan_table[AR40XX_MAX_VLANS];
2186 + u16 pvid[AR40XX_NUM_PORTS];
2195 +#define AR40XX_PORT_LINK_UP 1
2196 +#define AR40XX_PORT_LINK_DOWN 0
2197 +#define AR40XX_QM_NOT_EMPTY 1
2198 +#define AR40XX_QM_EMPTY 0
2200 +#define AR40XX_LAN_VLAN 1
2201 +#define AR40XX_WAN_VLAN 2
2203 +enum ar40xx_port_wrapper_cfg {
2204 + PORT_WRAPPER_PSGMII = 0,
2207 +struct ar40xx_mib_desc {
2213 +#define AR40XX_PORT_CPU 0
2215 +#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
2216 +#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
2218 +#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
2220 +#define AR40XX_MII_ATH_MMD_ADDR 0x0d
2221 +#define AR40XX_MII_ATH_MMD_DATA 0x0e
2222 +#define AR40XX_MII_ATH_DBG_ADDR 0x1d
2223 +#define AR40XX_MII_ATH_DBG_DATA 0x1e
2225 +#define AR40XX_STATS_RXBROAD 0x00
2226 +#define AR40XX_STATS_RXPAUSE 0x04
2227 +#define AR40XX_STATS_RXMULTI 0x08
2228 +#define AR40XX_STATS_RXFCSERR 0x0c
2229 +#define AR40XX_STATS_RXALIGNERR 0x10
2230 +#define AR40XX_STATS_RXRUNT 0x14
2231 +#define AR40XX_STATS_RXFRAGMENT 0x18
2232 +#define AR40XX_STATS_RX64BYTE 0x1c
2233 +#define AR40XX_STATS_RX128BYTE 0x20
2234 +#define AR40XX_STATS_RX256BYTE 0x24
2235 +#define AR40XX_STATS_RX512BYTE 0x28
2236 +#define AR40XX_STATS_RX1024BYTE 0x2c
2237 +#define AR40XX_STATS_RX1518BYTE 0x30
2238 +#define AR40XX_STATS_RXMAXBYTE 0x34
2239 +#define AR40XX_STATS_RXTOOLONG 0x38
2240 +#define AR40XX_STATS_RXGOODBYTE 0x3c
2241 +#define AR40XX_STATS_RXBADBYTE 0x44
2242 +#define AR40XX_STATS_RXOVERFLOW 0x4c
2243 +#define AR40XX_STATS_FILTERED 0x50
2244 +#define AR40XX_STATS_TXBROAD 0x54
2245 +#define AR40XX_STATS_TXPAUSE 0x58
2246 +#define AR40XX_STATS_TXMULTI 0x5c
2247 +#define AR40XX_STATS_TXUNDERRUN 0x60
2248 +#define AR40XX_STATS_TX64BYTE 0x64
2249 +#define AR40XX_STATS_TX128BYTE 0x68
2250 +#define AR40XX_STATS_TX256BYTE 0x6c
2251 +#define AR40XX_STATS_TX512BYTE 0x70
2252 +#define AR40XX_STATS_TX1024BYTE 0x74
2253 +#define AR40XX_STATS_TX1518BYTE 0x78
2254 +#define AR40XX_STATS_TXMAXBYTE 0x7c
2255 +#define AR40XX_STATS_TXOVERSIZE 0x80
2256 +#define AR40XX_STATS_TXBYTE 0x84
2257 +#define AR40XX_STATS_TXCOLLISION 0x8c
2258 +#define AR40XX_STATS_TXABORTCOL 0x90
2259 +#define AR40XX_STATS_TXMULTICOL 0x94
2260 +#define AR40XX_STATS_TXSINGLECOL 0x98
2261 +#define AR40XX_STATS_TXEXCDEFER 0x9c
2262 +#define AR40XX_STATS_TXDEFER 0xa0
2263 +#define AR40XX_STATS_TXLATECOL 0xa4
2265 +#define AR40XX_REG_MODULE_EN 0x030
2266 +#define AR40XX_MODULE_EN_MIB BIT(0)
2268 +#define AR40XX_REG_MIB_FUNC 0x034
2269 +#define AR40XX_MIB_BUSY BIT(17)
2270 +#define AR40XX_MIB_CPU_KEEP BIT(20)
2271 +#define AR40XX_MIB_FUNC BITS(24, 3)
2272 +#define AR40XX_MIB_FUNC_S 24
2273 +#define AR40XX_MIB_FUNC_NO_OP 0x0
2274 +#define AR40XX_MIB_FUNC_FLUSH 0x1
2276 +#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
2277 +#define AR40XX_PORT_SPEED BITS(0, 2)
2278 +#define AR40XX_PORT_STATUS_SPEED_S 0
2279 +#define AR40XX_PORT_TX_EN BIT(2)
2280 +#define AR40XX_PORT_RX_EN BIT(3)
2281 +#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
2282 +#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
2283 +#define AR40XX_PORT_DUPLEX BIT(6)
2284 +#define AR40XX_PORT_TXHALF_FLOW BIT(7)
2285 +#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
2286 +#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
2287 +#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
2289 +#define AR40XX_REG_MAX_FRAME_SIZE 0x078
2290 +#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
2292 +#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
2294 +#define AR40XX_REG_EEE_CTRL 0x100
2295 +#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
2297 +#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
2298 +#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
2299 +#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
2300 +#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
2301 +#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
2303 +#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
2304 +#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
2305 +#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
2306 +#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
2307 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
2308 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
2309 +#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
2310 +#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
2312 +#define AR40XX_REG_VTU_FUNC0 0x0610
2313 +#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
2314 +#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
2315 +#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
2316 +#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
2317 +#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
2318 +#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
2319 +#define AR40XX_VTU_FUNC0_IVL BIT(19)
2320 +#define AR40XX_VTU_FUNC0_VALID BIT(20)
2322 +#define AR40XX_REG_VTU_FUNC1 0x0614
2323 +#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
2324 +#define AR40XX_VTU_FUNC1_OP_NOOP 0
2325 +#define AR40XX_VTU_FUNC1_OP_FLUSH 1
2326 +#define AR40XX_VTU_FUNC1_OP_LOAD 2
2327 +#define AR40XX_VTU_FUNC1_OP_PURGE 3
2328 +#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
2329 +#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
2330 +#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
2331 +#define AR40XX_VTU_FUNC1_FULL BIT(4)
2332 +#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
2333 +#define AR40XX_VTU_FUNC1_PORT_S 8
2334 +#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
2335 +#define AR40XX_VTU_FUNC1_VID_S 16
2336 +#define AR40XX_VTU_FUNC1_BUSY BIT(31)
2338 +#define AR40XX_REG_FWD_CTRL0 0x620
2339 +#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
2340 +#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
2341 +#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
2343 +#define AR40XX_REG_FWD_CTRL1 0x624
2344 +#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
2345 +#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
2346 +#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
2347 +#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
2348 +#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
2349 +#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
2350 +#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
2351 +#define AR40XX_FWD_CTRL1_IGMP_S 24
2353 +#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
2354 +#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
2355 +#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
2356 +#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
2357 +#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
2358 +#define AR40XX_PORT_LOOKUP_STATE_S 16
2359 +#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
2360 +#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
2361 +#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
2363 +#define AR40XX_REG_ATU_FUNC 0x60c
2364 +#define AR40XX_ATU_FUNC_OP BITS(0, 4)
2365 +#define AR40XX_ATU_FUNC_OP_NOOP 0x0
2366 +#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
2367 +#define AR40XX_ATU_FUNC_OP_LOAD 0x2
2368 +#define AR40XX_ATU_FUNC_OP_PURGE 0x3
2369 +#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
2370 +#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
2371 +#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
2372 +#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
2373 +#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
2374 +#define AR40XX_ATU_FUNC_BUSY BIT(31)
2376 +#define AR40XX_REG_QM_DEBUG_ADDR 0x820
2377 +#define AR40XX_REG_QM_DEBUG_VALUE 0x824
2378 +#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
2379 +#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
2381 +#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
2382 +#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
2384 +#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
2385 +#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
2386 +#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
2388 +#define AR40XX_PHY_DEBUG_0 0
2389 +#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
2391 +#define AR40XX_PHY_DEBUG_2 2
2393 +#define AR40XX_PHY_SPEC_STATUS 0x11
2394 +#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
2395 +#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
2396 +#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
2398 +/* port forwarding state */
2400 + AR40XX_PORT_STATE_DISABLED = 0,
2401 + AR40XX_PORT_STATE_BLOCK = 1,
2402 + AR40XX_PORT_STATE_LISTEN = 2,
2403 + AR40XX_PORT_STATE_LEARN = 3,
2404 + AR40XX_PORT_STATE_FORWARD = 4
2407 +/* ingress 802.1q mode */
2409 + AR40XX_IN_PORT_ONLY = 0,
2410 + AR40XX_IN_PORT_FALLBACK = 1,
2411 + AR40XX_IN_VLAN_ONLY = 2,
2412 + AR40XX_IN_SECURE = 3
2415 +/* egress 802.1q mode */
2417 + AR40XX_OUT_KEEP = 0,
2418 + AR40XX_OUT_STRIP_VLAN = 1,
2419 + AR40XX_OUT_ADD_VLAN = 2
2424 + AR40XX_PORT_SPEED_10M = 0,
2425 + AR40XX_PORT_SPEED_100M = 1,
2426 + AR40XX_PORT_SPEED_1000M = 2,
2427 + AR40XX_PORT_SPEED_ERR = 3,
2430 +#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
2432 +#define AR40XX_QM_WORK_DELAY 100
2434 +#define AR40XX_MIB_FUNC_CAPTURE 0x3
2436 +#define AR40XX_REG_PORT_STATS_START 0x1000
2437 +#define AR40XX_REG_PORT_STATS_LEN 0x100
2439 +#define AR40XX_PORTS_ALL 0x3f
2441 +#define AR40XX_PSGMII_ID 5
2442 +#define AR40XX_PSGMII_CALB_NUM 100
2443 +#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
2444 +#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
2445 +#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
2446 +#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
2447 +#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
2448 +#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
2449 +#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
2450 +#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
2451 +#define AR40XX_MALIBU_PHY_LAST_ADDR 4
2453 +static inline struct ar40xx_priv *
2454 +swdev_to_ar40xx(struct switch_dev *swdev)
2456 + return container_of(swdev, struct ar40xx_priv, dev);