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ipq40xx: 6.6: refresh kernel patches
[openwrt/staging/nbd.git] / target / linux / ipq40xx / patches-6.6 / 706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch
1 From a38126870488398932e017dd9d76174b4aadbbbb Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robert.marko@sartura.hr>
3 Date: Sat, 10 Sep 2022 15:46:09 +0200
4 Subject: [PATCH] net: dsa: qca8k: add IPQ4019 built-in switch support
5
6 Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
7
8 It shares most of the stuff with its external counterpart, however it is
9 modified for the SoC.
10 Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
11 instead of 7.
12 It also has no built-in PHY-s but rather requires external PSGMII based
13 companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
14 out calibration before using them.
15 PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
16 unfortunately requires some magic values as the datasheet doesnt document
17 the bits that are being set or the register at all.
18
19 Since its built-in it is MMIO like other peripherals and doesn't have its
20 own MDIO bus but depends on the SoC provided one.
21
22 CPU connection is at Port 0 and it uses some kind of a internal connection
23 and no traditional RGMII/SGMII.
24
25 It also doesn't use in-band tagging like other qca8k switches so a out of
26 band based tagger is used.
27
28 Signed-off-by: Robert Marko <robert.marko@sartura.hr>
29 ---
30 drivers/net/dsa/qca/Kconfig | 8 +
31 drivers/net/dsa/qca/Makefile | 1 +
32 drivers/net/dsa/qca/qca8k-common.c | 6 +-
33 drivers/net/dsa/qca/qca8k-ipq4019.c | 948 ++++++++++++++++++++++++++++
34 drivers/net/dsa/qca/qca8k.h | 56 ++
35 5 files changed, 1016 insertions(+), 3 deletions(-)
36 create mode 100644 drivers/net/dsa/qca/qca8k-ipq4019.c
37
38 --- a/drivers/net/dsa/qca/Kconfig
39 +++ b/drivers/net/dsa/qca/Kconfig
40 @@ -24,3 +24,11 @@ config NET_DSA_QCA8K_LEDS_SUPPORT
41 help
42 This enabled support for LEDs present on the Qualcomm Atheros
43 QCA8K Ethernet switch chips.
44 +
45 +config NET_DSA_QCA8K_IPQ4019
46 + tristate "Qualcomm Atheros IPQ4019 Ethernet switch support"
47 + select NET_DSA_TAG_OOB
48 + select REGMAP_MMIO
49 + help
50 + This enables support for the switch built-into Qualcomm Atheros
51 + IPQ4019 SoCs.
52 --- a/drivers/net/dsa/qca/Makefile
53 +++ b/drivers/net/dsa/qca/Makefile
54 @@ -5,3 +5,4 @@ qca8k-y += qca8k-common.o qca8k-8xxx.
55 ifdef CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT
56 qca8k-y += qca8k-leds.o
57 endif
58 +obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o qca8k-common.o
59 --- a/drivers/net/dsa/qca/qca8k-common.c
60 +++ b/drivers/net/dsa/qca/qca8k-common.c
61 @@ -412,7 +412,7 @@ static int qca8k_vlan_del(struct qca8k_p
62
63 /* Check if we're the last member to be removed */
64 del = true;
65 - for (i = 0; i < QCA8K_NUM_PORTS; i++) {
66 + for (i = 0; i < priv->ds->num_ports; i++) {
67 mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
68
69 if ((reg & mask) != mask) {
70 @@ -653,7 +653,7 @@ int qca8k_port_bridge_join(struct dsa_sw
71 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
72 port_mask = BIT(cpu_port);
73
74 - for (i = 0; i < QCA8K_NUM_PORTS; i++) {
75 + for (i = 0; i < ds->num_ports; i++) {
76 if (dsa_is_cpu_port(ds, i))
77 continue;
78 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
79 @@ -685,7 +685,7 @@ void qca8k_port_bridge_leave(struct dsa_
80
81 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
82
83 - for (i = 0; i < QCA8K_NUM_PORTS; i++) {
84 + for (i = 0; i < ds->num_ports; i++) {
85 if (dsa_is_cpu_port(ds, i))
86 continue;
87 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
88 --- /dev/null
89 +++ b/drivers/net/dsa/qca/qca8k-ipq4019.c
90 @@ -0,0 +1,946 @@
91 +// SPDX-License-Identifier: GPL-2.0
92 +/*
93 + * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
94 + * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos <juhosg@openwrt.org>
95 + * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
96 + * Copyright (c) 2016 John Crispin <john@phrozen.org>
97 + * Copyright (c) 2022 Robert Marko <robert.marko@sartura.hr>
98 + */
99 +
100 +#include <linux/module.h>
101 +#include <linux/phy.h>
102 +#include <linux/netdevice.h>
103 +#include <linux/bitfield.h>
104 +#include <linux/regmap.h>
105 +#include <net/dsa.h>
106 +#include <linux/of_net.h>
107 +#include <linux/of_mdio.h>
108 +#include <linux/of_platform.h>
109 +#include <linux/mdio.h>
110 +#include <linux/phylink.h>
111 +
112 +#include "qca8k.h"
113 +
114 +static struct regmap_config qca8k_ipq4019_regmap_config = {
115 + .reg_bits = 32,
116 + .val_bits = 32,
117 + .reg_stride = 4,
118 + .max_register = 0x16ac, /* end MIB - Port6 range */
119 + .rd_table = &qca8k_readable_table,
120 +};
121 +
122 +static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config = {
123 + .name = "psgmii-phy",
124 + .reg_bits = 32,
125 + .val_bits = 32,
126 + .reg_stride = 4,
127 + .max_register = 0x7fc,
128 +};
129 +
130 +static enum dsa_tag_protocol
131 +qca8k_ipq4019_get_tag_protocol(struct dsa_switch *ds, int port,
132 + enum dsa_tag_protocol mp)
133 +{
134 + return DSA_TAG_PROTO_OOB;
135 +}
136 +
137 +static struct phylink_pcs *
138 +qca8k_ipq4019_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
139 + phy_interface_t interface)
140 +{
141 + struct qca8k_priv *priv = ds->priv;
142 + struct phylink_pcs *pcs = NULL;
143 +
144 + switch (interface) {
145 + case PHY_INTERFACE_MODE_PSGMII:
146 + switch (port) {
147 + case 0:
148 + pcs = &priv->pcs_port_0.pcs;
149 + break;
150 + }
151 + break;
152 + default:
153 + break;
154 + }
155 +
156 + return pcs;
157 +}
158 +
159 +static int qca8k_ipq4019_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
160 + phy_interface_t interface,
161 + const unsigned long *advertising,
162 + bool permit_pause_to_mac)
163 +{
164 + return 0;
165 +}
166 +
167 +static void qca8k_ipq4019_pcs_an_restart(struct phylink_pcs *pcs)
168 +{
169 +}
170 +
171 +static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
172 +{
173 + return container_of(pcs, struct qca8k_pcs, pcs);
174 +}
175 +
176 +static void qca8k_ipq4019_pcs_get_state(struct phylink_pcs *pcs,
177 + struct phylink_link_state *state)
178 +{
179 + struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
180 + int port = pcs_to_qca8k_pcs(pcs)->port;
181 + u32 reg;
182 + int ret;
183 +
184 + ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
185 + if (ret < 0) {
186 + state->link = false;
187 + return;
188 + }
189 +
190 + state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
191 + state->an_complete = state->link;
192 + state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
193 + DUPLEX_HALF;
194 +
195 + switch (reg & QCA8K_PORT_STATUS_SPEED) {
196 + case QCA8K_PORT_STATUS_SPEED_10:
197 + state->speed = SPEED_10;
198 + break;
199 + case QCA8K_PORT_STATUS_SPEED_100:
200 + state->speed = SPEED_100;
201 + break;
202 + case QCA8K_PORT_STATUS_SPEED_1000:
203 + state->speed = SPEED_1000;
204 + break;
205 + default:
206 + state->speed = SPEED_UNKNOWN;
207 + break;
208 + }
209 +
210 + if (reg & QCA8K_PORT_STATUS_RXFLOW)
211 + state->pause |= MLO_PAUSE_RX;
212 + if (reg & QCA8K_PORT_STATUS_TXFLOW)
213 + state->pause |= MLO_PAUSE_TX;
214 +}
215 +
216 +static const struct phylink_pcs_ops qca8k_pcs_ops = {
217 + .pcs_get_state = qca8k_ipq4019_pcs_get_state,
218 + .pcs_config = qca8k_ipq4019_pcs_config,
219 + .pcs_an_restart = qca8k_ipq4019_pcs_an_restart,
220 +};
221 +
222 +static void qca8k_ipq4019_setup_pcs(struct qca8k_priv *priv,
223 + struct qca8k_pcs *qpcs,
224 + int port)
225 +{
226 + qpcs->pcs.ops = &qca8k_pcs_ops;
227 +
228 + /* We don't have interrupts for link changes, so we need to poll */
229 + qpcs->pcs.poll = true;
230 + qpcs->priv = priv;
231 + qpcs->port = port;
232 +}
233 +
234 +static void qca8k_ipq4019_phylink_get_caps(struct dsa_switch *ds, int port,
235 + struct phylink_config *config)
236 +{
237 + switch (port) {
238 + case 0: /* CPU port */
239 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
240 + config->supported_interfaces);
241 + break;
242 +
243 + case 1:
244 + case 2:
245 + case 3:
246 + __set_bit(PHY_INTERFACE_MODE_PSGMII,
247 + config->supported_interfaces);
248 + break;
249 + case 4:
250 + case 5:
251 + phy_interface_set_rgmii(config->supported_interfaces);
252 + __set_bit(PHY_INTERFACE_MODE_PSGMII,
253 + config->supported_interfaces);
254 + break;
255 + }
256 +
257 + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
258 + MAC_10 | MAC_100 | MAC_1000FD;
259 +}
260 +
261 +static void
262 +qca8k_phylink_ipq4019_mac_link_down(struct dsa_switch *ds, int port,
263 + unsigned int mode,
264 + phy_interface_t interface)
265 +{
266 + struct qca8k_priv *priv = ds->priv;
267 +
268 + qca8k_port_set_status(priv, port, 0);
269 +}
270 +
271 +static void
272 +qca8k_phylink_ipq4019_mac_link_up(struct dsa_switch *ds, int port,
273 + unsigned int mode, phy_interface_t interface,
274 + struct phy_device *phydev, int speed,
275 + int duplex, bool tx_pause, bool rx_pause)
276 +{
277 + struct qca8k_priv *priv = ds->priv;
278 + u32 reg;
279 +
280 + if (phylink_autoneg_inband(mode)) {
281 + reg = QCA8K_PORT_STATUS_LINK_AUTO;
282 + } else {
283 + switch (speed) {
284 + case SPEED_10:
285 + reg = QCA8K_PORT_STATUS_SPEED_10;
286 + break;
287 + case SPEED_100:
288 + reg = QCA8K_PORT_STATUS_SPEED_100;
289 + break;
290 + case SPEED_1000:
291 + reg = QCA8K_PORT_STATUS_SPEED_1000;
292 + break;
293 + default:
294 + reg = QCA8K_PORT_STATUS_LINK_AUTO;
295 + break;
296 + }
297 +
298 + if (duplex == DUPLEX_FULL)
299 + reg |= QCA8K_PORT_STATUS_DUPLEX;
300 +
301 + if (rx_pause || dsa_is_cpu_port(ds, port))
302 + reg |= QCA8K_PORT_STATUS_RXFLOW;
303 +
304 + if (tx_pause || dsa_is_cpu_port(ds, port))
305 + reg |= QCA8K_PORT_STATUS_TXFLOW;
306 + }
307 +
308 + reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
309 +
310 + qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
311 +}
312 +
313 +static int psgmii_vco_calibrate(struct qca8k_priv *priv)
314 +{
315 + int val, ret;
316 +
317 + if (!priv->psgmii_ethphy) {
318 + dev_err(priv->dev, "PSGMII eth PHY missing, calibration failed!\n");
319 + return -ENODEV;
320 + }
321 +
322 + /* Fix PSGMII RX 20bit */
323 + ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
324 + /* Reset PHY PSGMII */
325 + ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x1b);
326 + /* Release PHY PSGMII reset */
327 + ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
328 +
329 + /* Poll for VCO PLL calibration finish - Malibu(QCA8075) */
330 + ret = phy_read_mmd_poll_timeout(priv->psgmii_ethphy,
331 + MDIO_MMD_PMAPMD,
332 + 0x28, val,
333 + (val & BIT(0)),
334 + 10000, 1000000,
335 + false);
336 + if (ret) {
337 + dev_err(priv->dev, "QCA807x PSGMII VCO calibration PLL not ready\n");
338 + return ret;
339 + }
340 + mdelay(50);
341 +
342 + /* Freeze PSGMII RX CDR */
343 + ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x2230);
344 +
345 + /* Start PSGMIIPHY VCO PLL calibration */
346 + ret = regmap_set_bits(priv->psgmii,
347 + PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1,
348 + PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART);
349 +
350 + /* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */
351 + ret = regmap_read_poll_timeout(priv->psgmii,
352 + PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2,
353 + val, val & PSGMIIPHY_REG_PLL_VCO_CALIB_READY,
354 + 10000, 1000000);
355 + if (ret) {
356 + dev_err(priv->dev, "IPQ PSGMIIPHY VCO calibration PLL not ready\n");
357 + return ret;
358 + }
359 + mdelay(50);
360 +
361 + /* Release PSGMII RX CDR */
362 + ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x3230);
363 + /* Release PSGMII RX 20bit */
364 + ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5f);
365 + mdelay(200);
366 +
367 + return ret;
368 +}
369 +
370 +static void
371 +qca8k_switch_port_loopback_on_off(struct qca8k_priv *priv, int port, int on)
372 +{
373 + u32 val = QCA8K_PORT_LOOKUP_LOOPBACK_EN;
374 +
375 + if (on == 0)
376 + val = 0;
377 +
378 + qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
379 + QCA8K_PORT_LOOKUP_LOOPBACK_EN, val);
380 +}
381 +
382 +static int
383 +qca8k_wait_for_phy_link_state(struct phy_device *phy, int need_status)
384 +{
385 + int a;
386 + u16 status;
387 +
388 + for (a = 0; a < 100; a++) {
389 + status = phy_read(phy, MII_QCA8075_SSTATUS);
390 + status &= QCA8075_PHY_SPEC_STATUS_LINK;
391 + status = !!status;
392 + if (status == need_status)
393 + return 0;
394 + mdelay(8);
395 + }
396 +
397 + return -1;
398 +}
399 +
400 +static void
401 +qca8k_phy_loopback_on_off(struct qca8k_priv *priv, struct phy_device *phy,
402 + int sw_port, int on)
403 +{
404 + if (on) {
405 + phy_write(phy, MII_BMCR, BMCR_ANENABLE | BMCR_RESET);
406 + phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
407 + qca8k_wait_for_phy_link_state(phy, 0);
408 + qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
409 + phy_write(phy, MII_BMCR,
410 + BMCR_SPEED1000 |
411 + BMCR_FULLDPLX |
412 + BMCR_LOOPBACK);
413 + qca8k_wait_for_phy_link_state(phy, 1);
414 + qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port),
415 + QCA8K_PORT_STATUS_SPEED_1000 |
416 + QCA8K_PORT_STATUS_TXMAC |
417 + QCA8K_PORT_STATUS_RXMAC |
418 + QCA8K_PORT_STATUS_DUPLEX);
419 + qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
420 + QCA8K_PORT_LOOKUP_STATE_FORWARD,
421 + QCA8K_PORT_LOOKUP_STATE_FORWARD);
422 + } else { /* off */
423 + qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
424 + qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
425 + QCA8K_PORT_LOOKUP_STATE_DISABLED,
426 + QCA8K_PORT_LOOKUP_STATE_DISABLED);
427 + phy_write(phy, MII_BMCR, BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_RESET);
428 + /* turn off the power of the phys - so that unused
429 + ports do not raise links */
430 + phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
431 + }
432 +}
433 +
434 +static void
435 +qca8k_phy_pkt_gen_prep(struct qca8k_priv *priv, struct phy_device *phy,
436 + int pkts_num, int on)
437 +{
438 + if (on) {
439 + /* enable CRC checker and packets counters */
440 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
441 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT,
442 + QCA8075_MMD7_CNT_FRAME_CHK_EN | QCA8075_MMD7_CNT_SELFCLR);
443 + qca8k_wait_for_phy_link_state(phy, 1);
444 + /* packet number */
445 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, pkts_num);
446 + /* pkt size - 1504 bytes + 20 bytes */
447 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_SIZE, 1504);
448 + } else { /* off */
449 + /* packet number */
450 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, 0);
451 + /* disable CRC checker and packet counter */
452 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
453 + /* disable traffic gen */
454 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, 0);
455 + }
456 +}
457 +
458 +static void
459 +qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv *priv, struct phy_device *phy)
460 +{
461 + int val;
462 + /* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */
463 + phy_read_mmd_poll_timeout(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
464 + val, !(val & QCA8075_MMD7_PKT_GEN_INPROGR),
465 + 50000, 1000000, true);
466 +}
467 +
468 +static void
469 +qca8k_start_phy_pkt_gen(struct phy_device *phy)
470 +{
471 + /* start traffic gen */
472 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
473 + QCA8075_MMD7_PKT_GEN_START | QCA8075_MMD7_PKT_GEN_INPROGR);
474 +}
475 +
476 +static int
477 +qca8k_start_all_phys_pkt_gens(struct qca8k_priv *priv)
478 +{
479 + struct phy_device *phy;
480 + phy = phy_device_create(priv->bus, QCA8075_MDIO_BRDCST_PHY_ADDR,
481 + 0, 0, NULL);
482 + if (!phy) {
483 + dev_err(priv->dev, "unable to create mdio broadcast PHY(0x%x)\n",
484 + QCA8075_MDIO_BRDCST_PHY_ADDR);
485 + return -ENODEV;
486 + }
487 +
488 + qca8k_start_phy_pkt_gen(phy);
489 +
490 + phy_device_free(phy);
491 + return 0;
492 +}
493 +
494 +static int
495 +qca8k_get_phy_pkt_gen_test_result(struct phy_device *phy, int pkts_num)
496 +{
497 + u32 tx_ok, tx_error;
498 + u32 rx_ok, rx_error;
499 + u32 tx_ok_high16;
500 + u32 rx_ok_high16;
501 + u32 tx_all_ok, rx_all_ok;
502 +
503 + /* check counters */
504 + tx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO);
505 + tx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI);
506 + tx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_ERR_CNT);
507 + rx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO);
508 + rx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI);
509 + rx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_ERR_CNT);
510 + tx_all_ok = tx_ok + (tx_ok_high16 << 16);
511 + rx_all_ok = rx_ok + (rx_ok_high16 << 16);
512 +
513 + if (tx_all_ok < pkts_num)
514 + return -1;
515 + if(rx_all_ok < pkts_num)
516 + return -2;
517 + if(tx_error)
518 + return -3;
519 + if(rx_error)
520 + return -4;
521 + return 0; /* test is ok */
522 +}
523 +
524 +static
525 +void qca8k_phy_broadcast_write_on_off(struct qca8k_priv *priv,
526 + struct phy_device *phy, int on)
527 +{
528 + u32 val;
529 +
530 + val = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE);
531 +
532 + if (on == 0)
533 + val &= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
534 + else
535 + val |= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
536 +
537 + phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE, val);
538 +}
539 +
540 +static int
541 +qca8k_test_dsa_port_for_errors(struct qca8k_priv *priv, struct phy_device *phy,
542 + int port, int test_phase)
543 +{
544 + int res = 0;
545 + const int test_pkts_num = QCA8075_PKT_GEN_PKTS_COUNT;
546 +
547 + if (test_phase == 1) { /* start test preps */
548 + qca8k_phy_loopback_on_off(priv, phy, port, 1);
549 + qca8k_switch_port_loopback_on_off(priv, port, 1);
550 + qca8k_phy_broadcast_write_on_off(priv, phy, 1);
551 + qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 1);
552 + } else if (test_phase == 2) {
553 + /* wait for test results, collect it and cleanup */
554 + qca8k_wait_for_phy_pkt_gen_fin(priv, phy);
555 + res = qca8k_get_phy_pkt_gen_test_result(phy, test_pkts_num);
556 + qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 0);
557 + qca8k_phy_broadcast_write_on_off(priv, phy, 0);
558 + qca8k_switch_port_loopback_on_off(priv, port, 0);
559 + qca8k_phy_loopback_on_off(priv, phy, port, 0);
560 + }
561 +
562 + return res;
563 +}
564 +
565 +static int
566 +qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv *priv, int parallel_test)
567 +{
568 + struct device_node *dn = priv->dev->of_node;
569 + struct device_node *ports, *port;
570 + struct device_node *phy_dn;
571 + struct phy_device *phy;
572 + int reg, err = 0, test_phase;
573 + u32 tests_result = 0;
574 +
575 + ports = of_get_child_by_name(dn, "ports");
576 + if (!ports) {
577 + dev_err(priv->dev, "no ports child node found\n");
578 + return -EINVAL;
579 + }
580 +
581 + for (test_phase = 1; test_phase <= 2; test_phase++) {
582 + if (parallel_test && test_phase == 2) {
583 + err = qca8k_start_all_phys_pkt_gens(priv);
584 + if (err)
585 + goto error;
586 + }
587 + for_each_available_child_of_node(ports, port) {
588 + err = of_property_read_u32(port, "reg", &reg);
589 + if (err)
590 + goto error;
591 + if (reg >= QCA8K_NUM_PORTS) {
592 + err = -EINVAL;
593 + goto error;
594 + }
595 + phy_dn = of_parse_phandle(port, "phy-handle", 0);
596 + if (phy_dn) {
597 + phy = of_phy_find_device(phy_dn);
598 + of_node_put(phy_dn);
599 + if (phy) {
600 + int result;
601 + result = qca8k_test_dsa_port_for_errors(priv,
602 + phy, reg, test_phase);
603 + if (!parallel_test && test_phase == 1)
604 + qca8k_start_phy_pkt_gen(phy);
605 + put_device(&phy->mdio.dev);
606 + if (test_phase == 2) {
607 + tests_result <<= 1;
608 + if (result)
609 + tests_result |= 1;
610 + }
611 + }
612 + }
613 + }
614 + }
615 +
616 +end:
617 + of_node_put(ports);
618 + qca8k_fdb_flush(priv);
619 + return tests_result;
620 +error:
621 + tests_result |= 0xf000;
622 + goto end;
623 +}
624 +
625 +static int
626 +psgmii_vco_calibrate_and_test(struct dsa_switch *ds)
627 +{
628 + int ret, a, test_result;
629 + struct qca8k_priv *priv = ds->priv;
630 +
631 + for (a = 0; a <= QCA8K_PSGMII_CALB_NUM; a++) {
632 + ret = psgmii_vco_calibrate(priv);
633 + if (ret)
634 + return ret;
635 + /* first we run serial test */
636 + test_result = qca8k_do_dsa_sw_ports_self_test(priv, 0);
637 + /* and if it is ok then we run the test in parallel */
638 + if (!test_result)
639 + test_result = qca8k_do_dsa_sw_ports_self_test(priv, 1);
640 + if (!test_result) {
641 + if (a > 0) {
642 + dev_warn(priv->dev, "PSGMII work was stabilized after %d "
643 + "calibration retries !\n", a);
644 + }
645 + return 0;
646 + } else {
647 + schedule();
648 + if (a > 0 && a % 10 == 0) {
649 + dev_err(priv->dev, "PSGMII work is unstable !!! "
650 + "Let's try to wait a bit ... %d\n", a);
651 + set_current_state(TASK_INTERRUPTIBLE);
652 + schedule_timeout(msecs_to_jiffies(a * 100));
653 + }
654 + }
655 + }
656 +
657 + panic("PSGMII work is unstable !!! "
658 + "Repeated recalibration attempts did not help(0x%x) !\n",
659 + test_result);
660 +
661 + return -EFAULT;
662 +}
663 +
664 +static int
665 +ipq4019_psgmii_configure(struct dsa_switch *ds)
666 +{
667 + struct qca8k_priv *priv = ds->priv;
668 + int ret;
669 +
670 + if (!priv->psgmii_calibrated) {
671 + dev_info(ds->dev, "PSGMII calibration!\n");
672 + ret = psgmii_vco_calibrate_and_test(ds);
673 +
674 + ret = regmap_clear_bits(priv->psgmii, PSGMIIPHY_MODE_CONTROL,
675 + PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M);
676 + ret = regmap_write(priv->psgmii, PSGMIIPHY_TX_CONTROL,
677 + PSGMIIPHY_TX_CONTROL_MAGIC_VALUE);
678 +
679 + priv->psgmii_calibrated = true;
680 +
681 + return ret;
682 + }
683 +
684 + return 0;
685 +}
686 +
687 +static void
688 +qca8k_phylink_ipq4019_mac_config(struct dsa_switch *ds, int port,
689 + unsigned int mode,
690 + const struct phylink_link_state *state)
691 +{
692 + struct qca8k_priv *priv = ds->priv;
693 +
694 + switch (port) {
695 + case 0:
696 + /* CPU port, no configuration needed */
697 + return;
698 + case 1:
699 + case 2:
700 + case 3:
701 + if (state->interface == PHY_INTERFACE_MODE_PSGMII)
702 + if (ipq4019_psgmii_configure(ds))
703 + dev_err(ds->dev, "PSGMII configuration failed!\n");
704 + return;
705 + case 4:
706 + case 5:
707 + if (state->interface == PHY_INTERFACE_MODE_RGMII ||
708 + state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
709 + state->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
710 + state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
711 + regmap_set_bits(priv->regmap,
712 + QCA8K_IPQ4019_REG_RGMII_CTRL,
713 + QCA8K_IPQ4019_RGMII_CTRL_CLK);
714 + }
715 +
716 + if (state->interface == PHY_INTERFACE_MODE_PSGMII)
717 + if (ipq4019_psgmii_configure(ds))
718 + dev_err(ds->dev, "PSGMII configuration failed!\n");
719 + return;
720 + default:
721 + dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
722 + return;
723 + }
724 +}
725 +
726 +static int
727 +qca8k_ipq4019_setup_port(struct dsa_switch *ds, int port)
728 +{
729 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
730 + int ret;
731 +
732 + /* CPU port gets connected to all user ports of the switch */
733 + if (dsa_is_cpu_port(ds, port)) {
734 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
735 + QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
736 + if (ret)
737 + return ret;
738 +
739 + /* Disable CPU ARP Auto-learning by default */
740 + ret = regmap_clear_bits(priv->regmap,
741 + QCA8K_PORT_LOOKUP_CTRL(port),
742 + QCA8K_PORT_LOOKUP_LEARN);
743 + if (ret)
744 + return ret;
745 + }
746 +
747 + /* Individual user ports get connected to CPU port only */
748 + if (dsa_is_user_port(ds, port)) {
749 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
750 + QCA8K_PORT_LOOKUP_MEMBER,
751 + BIT(QCA8K_IPQ4019_CPU_PORT));
752 + if (ret)
753 + return ret;
754 +
755 + /* Enable ARP Auto-learning by default */
756 + ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(port),
757 + QCA8K_PORT_LOOKUP_LEARN);
758 + if (ret)
759 + return ret;
760 +
761 + /* For port based vlans to work we need to set the
762 + * default egress vid
763 + */
764 + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
765 + QCA8K_EGREES_VLAN_PORT_MASK(port),
766 + QCA8K_EGREES_VLAN_PORT(port, QCA8K_PORT_VID_DEF));
767 + if (ret)
768 + return ret;
769 +
770 + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
771 + QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
772 + QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
773 + if (ret)
774 + return ret;
775 + }
776 +
777 + return 0;
778 +}
779 +
780 +static int
781 +qca8k_ipq4019_setup(struct dsa_switch *ds)
782 +{
783 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
784 + int ret, i;
785 +
786 + /* Make sure that port 0 is the cpu port */
787 + if (!dsa_is_cpu_port(ds, QCA8K_IPQ4019_CPU_PORT)) {
788 + dev_err(priv->dev, "port %d is not the CPU port",
789 + QCA8K_IPQ4019_CPU_PORT);
790 + return -EINVAL;
791 + }
792 +
793 + qca8k_ipq4019_setup_pcs(priv, &priv->pcs_port_0, 0);
794 +
795 + /* Enable CPU Port */
796 + ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
797 + QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
798 + if (ret) {
799 + dev_err(priv->dev, "failed enabling CPU port");
800 + return ret;
801 + }
802 +
803 + /* Enable MIB counters */
804 + ret = qca8k_mib_init(priv);
805 + if (ret)
806 + dev_warn(priv->dev, "MIB init failed");
807 +
808 + /* Disable forwarding by default on all ports */
809 + for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
810 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
811 + QCA8K_PORT_LOOKUP_MEMBER, 0);
812 + if (ret)
813 + return ret;
814 + }
815 +
816 + /* Enable QCA header mode on the CPU port */
817 + ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_IPQ4019_CPU_PORT),
818 + FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
819 + FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
820 + if (ret) {
821 + dev_err(priv->dev, "failed enabling QCA header mode");
822 + return ret;
823 + }
824 +
825 + /* Disable MAC by default on all ports */
826 + for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
827 + if (dsa_is_user_port(ds, i))
828 + qca8k_port_set_status(priv, i, 0);
829 + }
830 +
831 + /* Forward all unknown frames to CPU port for Linux processing */
832 + ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
833 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
834 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
835 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
836 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)));
837 + if (ret)
838 + return ret;
839 +
840 + /* Setup connection between CPU port & user ports */
841 + for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
842 + ret = qca8k_ipq4019_setup_port(ds, i);
843 + if (ret)
844 + return ret;
845 + }
846 +
847 + /* Setup our port MTUs to match power on defaults */
848 + ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
849 + if (ret)
850 + dev_warn(priv->dev, "failed setting MTU settings");
851 +
852 + /* Flush the FDB table */
853 + qca8k_fdb_flush(priv);
854 +
855 + /* Set min a max ageing value supported */
856 + ds->ageing_time_min = 7000;
857 + ds->ageing_time_max = 458745000;
858 +
859 + /* Set max number of LAGs supported */
860 + ds->num_lag_ids = QCA8K_NUM_LAGS;
861 +
862 + /* CPU port HW learning doesnt work correctly, so let DSA handle it */
863 + ds->assisted_learning_on_cpu_port = true;
864 +
865 + return 0;
866 +}
867 +
868 +static const struct dsa_switch_ops qca8k_ipq4019_switch_ops = {
869 + .get_tag_protocol = qca8k_ipq4019_get_tag_protocol,
870 + .setup = qca8k_ipq4019_setup,
871 + .get_strings = qca8k_get_strings,
872 + .get_ethtool_stats = qca8k_get_ethtool_stats,
873 + .get_sset_count = qca8k_get_sset_count,
874 + .set_ageing_time = qca8k_set_ageing_time,
875 + .get_mac_eee = qca8k_get_mac_eee,
876 + .set_mac_eee = qca8k_set_mac_eee,
877 + .port_enable = qca8k_port_enable,
878 + .port_disable = qca8k_port_disable,
879 + .port_change_mtu = qca8k_port_change_mtu,
880 + .port_max_mtu = qca8k_port_max_mtu,
881 + .port_stp_state_set = qca8k_port_stp_state_set,
882 + .port_bridge_join = qca8k_port_bridge_join,
883 + .port_bridge_leave = qca8k_port_bridge_leave,
884 + .port_fast_age = qca8k_port_fast_age,
885 + .port_fdb_add = qca8k_port_fdb_add,
886 + .port_fdb_del = qca8k_port_fdb_del,
887 + .port_fdb_dump = qca8k_port_fdb_dump,
888 + .port_mdb_add = qca8k_port_mdb_add,
889 + .port_mdb_del = qca8k_port_mdb_del,
890 + .port_mirror_add = qca8k_port_mirror_add,
891 + .port_mirror_del = qca8k_port_mirror_del,
892 + .port_vlan_filtering = qca8k_port_vlan_filtering,
893 + .port_vlan_add = qca8k_port_vlan_add,
894 + .port_vlan_del = qca8k_port_vlan_del,
895 + .phylink_mac_select_pcs = qca8k_ipq4019_phylink_mac_select_pcs,
896 + .phylink_get_caps = qca8k_ipq4019_phylink_get_caps,
897 + .phylink_mac_config = qca8k_phylink_ipq4019_mac_config,
898 + .phylink_mac_link_down = qca8k_phylink_ipq4019_mac_link_down,
899 + .phylink_mac_link_up = qca8k_phylink_ipq4019_mac_link_up,
900 + .port_lag_join = qca8k_port_lag_join,
901 + .port_lag_leave = qca8k_port_lag_leave,
902 +};
903 +
904 +static const struct qca8k_match_data ipq4019 = {
905 + .id = QCA8K_ID_IPQ4019,
906 + .mib_count = QCA8K_QCA833X_MIB_COUNT,
907 +};
908 +
909 +static int
910 +qca8k_ipq4019_probe(struct platform_device *pdev)
911 +{
912 + struct device *dev = &pdev->dev;
913 + struct qca8k_priv *priv;
914 + void __iomem *base, *psgmii;
915 + struct device_node *np = dev->of_node, *mdio_np, *psgmii_ethphy_np;
916 + int ret;
917 +
918 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
919 + if (!priv)
920 + return -ENOMEM;
921 +
922 + priv->dev = dev;
923 + priv->info = &ipq4019;
924 +
925 + /* Start by setting up the register mapping */
926 + base = devm_platform_ioremap_resource_byname(pdev, "base");
927 + if (IS_ERR(base))
928 + return PTR_ERR(base);
929 +
930 + priv->regmap = devm_regmap_init_mmio(dev, base,
931 + &qca8k_ipq4019_regmap_config);
932 + if (IS_ERR(priv->regmap)) {
933 + ret = PTR_ERR(priv->regmap);
934 + dev_err(dev, "base regmap initialization failed, %d\n", ret);
935 + return ret;
936 + }
937 +
938 + psgmii = devm_platform_ioremap_resource_byname(pdev, "psgmii_phy");
939 + if (IS_ERR(psgmii))
940 + return PTR_ERR(psgmii);
941 +
942 + priv->psgmii = devm_regmap_init_mmio(dev, psgmii,
943 + &qca8k_ipq4019_psgmii_phy_regmap_config);
944 + if (IS_ERR(priv->psgmii)) {
945 + ret = PTR_ERR(priv->psgmii);
946 + dev_err(dev, "PSGMII regmap initialization failed, %d\n", ret);
947 + return ret;
948 + }
949 +
950 + mdio_np = of_parse_phandle(np, "mdio", 0);
951 + if (!mdio_np) {
952 + dev_err(dev, "unable to get MDIO bus phandle\n");
953 + of_node_put(mdio_np);
954 + return -EINVAL;
955 + }
956 +
957 + priv->bus = of_mdio_find_bus(mdio_np);
958 + of_node_put(mdio_np);
959 + if (!priv->bus) {
960 + dev_err(dev, "unable to find MDIO bus\n");
961 + return -EPROBE_DEFER;
962 + }
963 +
964 + psgmii_ethphy_np = of_parse_phandle(np, "psgmii-ethphy", 0);
965 + if (!psgmii_ethphy_np) {
966 + dev_dbg(dev, "unable to get PSGMII eth PHY phandle\n");
967 + of_node_put(psgmii_ethphy_np);
968 + }
969 +
970 + if (psgmii_ethphy_np) {
971 + priv->psgmii_ethphy = of_phy_find_device(psgmii_ethphy_np);
972 + of_node_put(psgmii_ethphy_np);
973 + if (!priv->psgmii_ethphy) {
974 + dev_err(dev, "unable to get PSGMII eth PHY\n");
975 + return -ENODEV;
976 + }
977 + }
978 +
979 + /* Check the detected switch id */
980 + ret = qca8k_read_switch_id(priv);
981 + if (ret)
982 + return ret;
983 +
984 + priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
985 + if (!priv->ds)
986 + return -ENOMEM;
987 +
988 + priv->ds->dev = dev;
989 + priv->ds->num_ports = QCA8K_IPQ4019_NUM_PORTS;
990 + priv->ds->priv = priv;
991 + priv->ds->ops = &qca8k_ipq4019_switch_ops;
992 + mutex_init(&priv->reg_mutex);
993 + platform_set_drvdata(pdev, priv);
994 +
995 + return dsa_register_switch(priv->ds);
996 +}
997 +
998 +static int
999 +qca8k_ipq4019_remove(struct platform_device *pdev)
1000 +{
1001 + struct qca8k_priv *priv = dev_get_drvdata(&pdev->dev);
1002 + int i;
1003 +
1004 + if (!priv)
1005 + return 0;
1006 +
1007 + for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++)
1008 + qca8k_port_set_status(priv, i, 0);
1009 +
1010 + dsa_unregister_switch(priv->ds);
1011 +
1012 + platform_set_drvdata(pdev, NULL);
1013 +
1014 + return 0;
1015 +}
1016 +
1017 +static const struct of_device_id qca8k_ipq4019_of_match[] = {
1018 + { .compatible = "qca,ipq4019-qca8337n", },
1019 + { /* sentinel */ },
1020 +};
1021 +
1022 +static struct platform_driver qca8k_ipq4019_driver = {
1023 + .probe = qca8k_ipq4019_probe,
1024 + .remove = qca8k_ipq4019_remove,
1025 + .driver = {
1026 + .name = "qca8k-ipq4019",
1027 + .of_match_table = qca8k_ipq4019_of_match,
1028 + },
1029 +};
1030 +
1031 +module_platform_driver(qca8k_ipq4019_driver);
1032 +
1033 +MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1034 +MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>, Robert Marko <robert.marko@sartura.hr>");
1035 +MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver");
1036 +MODULE_LICENSE("GPL");
1037 --- a/drivers/net/dsa/qca/qca8k.h
1038 +++ b/drivers/net/dsa/qca/qca8k.h
1039 @@ -19,7 +19,10 @@
1040 #define QCA8K_ETHERNET_TIMEOUT 5
1041
1042 #define QCA8K_NUM_PORTS 7
1043 +#define QCA8K_IPQ4019_NUM_PORTS 6
1044 #define QCA8K_NUM_CPU_PORTS 2
1045 +#define QCA8K_IPQ4019_NUM_CPU_PORTS 1
1046 +#define QCA8K_IPQ4019_CPU_PORT 0
1047 #define QCA8K_MAX_MTU 9000
1048 #define QCA8K_NUM_LAGS 4
1049 #define QCA8K_NUM_PORTS_FOR_LAG 4
1050 @@ -28,6 +31,7 @@
1051 #define QCA8K_ID_QCA8327 0x12
1052 #define PHY_ID_QCA8337 0x004dd036
1053 #define QCA8K_ID_QCA8337 0x13
1054 +#define QCA8K_ID_IPQ4019 0x14
1055
1056 #define QCA8K_QCA832X_MIB_COUNT 39
1057 #define QCA8K_QCA833X_MIB_COUNT 41
1058 @@ -265,6 +269,7 @@
1059 #define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
1060 #define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
1061 #define QCA8K_PORT_LOOKUP_LEARN BIT(20)
1062 +#define QCA8K_PORT_LOOKUP_LOOPBACK_EN BIT(21)
1063 #define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
1064
1065 #define QCA8K_REG_GOL_TRUNK_CTRL0 0x700
1066 @@ -341,6 +346,53 @@
1067 #define MII_ATH_MMD_ADDR 0x0d
1068 #define MII_ATH_MMD_DATA 0x0e
1069
1070 +/* IPQ4019 PSGMII PHY registers */
1071 +#define QCA8K_IPQ4019_REG_RGMII_CTRL 0x004
1072 +#define QCA8K_IPQ4019_RGMII_CTRL_RGMII_RXC GENMASK(1, 0)
1073 +#define QCA8K_IPQ4019_RGMII_CTRL_RGMII_TXC GENMASK(9, 8)
1074 +/* Some kind of CLK selection
1075 + * 0: gcc_ess_dly2ns
1076 + * 1: gcc_ess_clk
1077 + */
1078 +#define QCA8K_IPQ4019_RGMII_CTRL_CLK BIT(10)
1079 +#define QCA8K_IPQ4019_RGMII_CTRL_DELAY_RMII0 GENMASK(17, 16)
1080 +#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII0_REF_CLK BIT(18)
1081 +#define QCA8K_IPQ4019_RGMII_CTRL_DELAY_RMII1 GENMASK(20, 19)
1082 +#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII1_REF_CLK BIT(21)
1083 +#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII0_MASTER_EN BIT(24)
1084 +#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII1_MASTER_EN BIT(25)
1085 +
1086 +#define PSGMIIPHY_MODE_CONTROL 0x1b4
1087 +#define PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M BIT(0)
1088 +#define PSGMIIPHY_TX_CONTROL 0x288
1089 +#define PSGMIIPHY_TX_CONTROL_MAGIC_VALUE 0x8380
1090 +#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1 0x9c
1091 +#define PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART BIT(14)
1092 +#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2 0xa0
1093 +#define PSGMIIPHY_REG_PLL_VCO_CALIB_READY BIT(0)
1094 +
1095 +#define QCA8K_PSGMII_CALB_NUM 100
1096 +#define MII_QCA8075_SSTATUS 0x11
1097 +#define QCA8075_PHY_SPEC_STATUS_LINK BIT(10)
1098 +#define QCA8075_MMD7_CRC_AND_PKTS_COUNT 0x8029
1099 +#define QCA8075_MMD7_PKT_GEN_PKT_NUMB 0x8021
1100 +#define QCA8075_MMD7_PKT_GEN_PKT_SIZE 0x8062
1101 +#define QCA8075_MMD7_PKT_GEN_CTRL 0x8020
1102 +#define QCA8075_MMD7_CNT_SELFCLR BIT(1)
1103 +#define QCA8075_MMD7_CNT_FRAME_CHK_EN BIT(0)
1104 +#define QCA8075_MMD7_PKT_GEN_START BIT(13)
1105 +#define QCA8075_MMD7_PKT_GEN_INPROGR BIT(15)
1106 +#define QCA8075_MMD7_IG_FRAME_RECV_CNT_HI 0x802a
1107 +#define QCA8075_MMD7_IG_FRAME_RECV_CNT_LO 0x802b
1108 +#define QCA8075_MMD7_IG_FRAME_ERR_CNT 0x802c
1109 +#define QCA8075_MMD7_EG_FRAME_RECV_CNT_HI 0x802d
1110 +#define QCA8075_MMD7_EG_FRAME_RECV_CNT_LO 0x802e
1111 +#define QCA8075_MMD7_EG_FRAME_ERR_CNT 0x802f
1112 +#define QCA8075_MMD7_MDIO_BRDCST_WRITE 0x8028
1113 +#define QCA8075_MMD7_MDIO_BRDCST_WRITE_EN BIT(15)
1114 +#define QCA8075_MDIO_BRDCST_PHY_ADDR 0x1f
1115 +#define QCA8075_PKT_GEN_PKTS_COUNT 4096
1116 +
1117 enum {
1118 QCA8K_PORT_SPEED_10M = 0,
1119 QCA8K_PORT_SPEED_100M = 1,
1120 @@ -466,6 +518,10 @@ struct qca8k_priv {
1121 struct qca8k_pcs pcs_port_6;
1122 const struct qca8k_match_data *info;
1123 struct qca8k_led ports_led[QCA8K_LED_COUNT];
1124 + /* IPQ4019 specific */
1125 + struct regmap *psgmii;
1126 + struct phy_device *psgmii_ethphy;
1127 + bool psgmii_calibrated;
1128 };
1129
1130 struct qca8k_mib_desc {
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