1 #include "qcom-ipq8064-v2.0-smb208.dtsi"
3 #include <dt-bindings/input/input.h>
6 model = "Netgear Nighthawk X4 D7800";
7 compatible = "netgear,d7800", "qcom,ipq8064";
10 reg = <0x42000000 0x1e000000>;
11 device_type = "memory";
16 reg = <0x5fe00000 0x200000>;
24 led-boot = &power_white;
25 led-failsafe = &power_amber;
26 led-running = &power_white;
27 led-upgrade = &power_amber;
31 bootargs = "rootfstype=squashfs noinitrd";
35 compatible = "gpio-keys";
36 pinctrl-0 = <&button_pins>;
37 pinctrl-names = "default";
41 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_RFKILL>;
43 debounce-interval = <60>;
49 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
50 linux,code = <KEY_RESTART>;
51 debounce-interval = <60>;
57 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
58 linux,code = <KEY_WPS_BUTTON>;
59 debounce-interval = <60>;
65 compatible = "gpio-leds";
66 pinctrl-0 = <&led_pins>;
67 pinctrl-names = "default";
71 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
76 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
79 power_amber: power_amber {
80 label = "amber:power";
81 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
86 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
91 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
96 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
100 label = "white:esata";
101 gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
104 power_white: power_white {
105 label = "white:power";
106 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
107 default-state = "keep";
111 label = "white:wifi";
112 gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
118 button_pins: button_pins {
120 pins = "gpio6", "gpio54", "gpio65";
122 drive-strength = <2>;
129 pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
130 "gpio24","gpio26", "gpio53", "gpio64";
132 drive-strength = <2>;
137 usb0_pwr_en_pins: usb0_pwr_en_pins {
141 drive-strength = <12>;
147 usb1_pwr_en_pins: usb1_pwr_en_pins {
149 pins = "gpio16", "gpio68";
151 drive-strength = <12>;
177 pinctrl-0 = <&usb0_pwr_en_pins>;
178 pinctrl-names = "default";
192 pinctrl-0 = <&usb1_pwr_en_pins>;
193 pinctrl-names = "default";
198 reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
199 pinctrl-0 = <&pcie0_pins>;
200 pinctrl-names = "default";
203 reg = <0x00000000 0 0 0 0>;
204 #address-cells = <3>;
209 compatible = "pci168c,0040";
210 reg = <0x00010000 0 0 0 0>;
212 nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
213 nvmem-cell-names = "mac-address", "pre-calibration";
214 mac-address-increment = <(1)>;
221 reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
222 pinctrl-0 = <&pcie1_pins>;
223 pinctrl-names = "default";
224 max-link-speed = <1>;
227 reg = <0x00000000 0 0 0 0>;
228 #address-cells = <3>;
233 compatible = "pci168c,0040";
234 reg = <0x00010000 0 0 0 0>;
236 nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
237 nvmem-cell-names = "mac-address", "pre-calibration";
238 mac-address-increment = <(2)>;
245 reset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
246 pinctrl-0 = <&pcie2_pins>;
247 pinctrl-names = "default";
255 compatible = "qcom,nandcs";
257 nand-ecc-strength = <4>;
258 nand-bus-width = <8>;
259 nand-ecc-step-size = <512>;
262 qcom,boot-partitions = <0x0 0x1180000>;
265 compatible = "fixed-partitions";
266 #address-cells = <1>;
271 reg = <0x0000000 0x0c80000>;
277 reg = <0x0c80000 0x0500000>;
283 reg = <0x1180000 0x0080000>;
289 reg = <0x1200000 0x0140000>;
291 compatible = "nvmem-cells";
292 #address-cells = <1>;
295 macaddr_art_0: macaddr@0 {
299 macaddr_art_6: macaddr@6 {
303 precal_art_1000: precal@1000 {
304 reg = <0x1000 0x2f20>;
307 precal_art_5000: precal@5000 {
308 reg = <0x5000 0x2f20>;
312 artbak: art@1340000 {
314 reg = <0x1340000 0x0140000>;
320 reg = <0x1480000 0x0400000>;
325 reg = <0x1880000 0x6080000>;
330 reg = <0x7900000 0x0700000>;
340 pinctrl-0 = <&mdio0_pins>;
341 pinctrl-names = "default";
344 compatible = "qca,qca8337";
345 #address-cells = <1>;
350 #address-cells = <1>;
358 tx-internal-delay-ps = <1000>;
359 rx-internal-delay-ps = <1000>;
370 phy-mode = "internal";
371 phy-handle = <&phy_port1>;
377 phy-mode = "internal";
378 phy-handle = <&phy_port2>;
384 phy-mode = "internal";
385 phy-handle = <&phy_port3>;
391 phy-mode = "internal";
392 phy-handle = <&phy_port4>;
398 phy-mode = "internal";
399 phy-handle = <&phy_port5>;
407 qca,sgmii-enable-pll;
417 #address-cells = <1>;
448 pinctrl-0 = <&rgmii2_pins>;
449 pinctrl-names = "default";
451 nvmem-cells = <&macaddr_art_6>;
452 nvmem-cell-names = "mac-address";
465 nvmem-cells = <&macaddr_art_0>;
466 nvmem-cell-names = "mac-address";