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[openwrt/staging/hauke.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065-nighthawk.dtsi
1 #include "qcom-ipq8065.dtsi"
2
3 #include <dt-bindings/input/input.h>
4
5 / {
6 memory@0 {
7 reg = <0x42000000 0x1e000000>;
8 device_type = "memory";
9 };
10
11 reserved-memory {
12 rsvd@5fe00000 {
13 reg = <0x5fe00000 0x200000>;
14 reusable;
15 };
16 };
17
18 aliases {
19 label-mac-device = &gmac2;
20
21 led-boot = &power_white;
22 led-failsafe = &power_amber;
23 led-running = &power_white;
24 led-upgrade = &power_amber;
25
26 mdio-gpio0 = &mdio0;
27 };
28
29 keys {
30 compatible = "gpio-keys";
31 pinctrl-0 = <&button_pins>;
32 pinctrl-names = "default";
33
34 wifi {
35 label = "wifi";
36 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
37 linux,code = <KEY_RFKILL>;
38 debounce-interval = <60>;
39 wakeup-source;
40 };
41
42 reset {
43 label = "reset";
44 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
45 linux,code = <KEY_RESTART>;
46 debounce-interval = <60>;
47 wakeup-source;
48 };
49
50 wps {
51 label = "wps";
52 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
53 linux,code = <KEY_WPS_BUTTON>;
54 debounce-interval = <60>;
55 wakeup-source;
56 };
57 };
58
59 leds: leds {
60 compatible = "gpio-leds";
61 pinctrl-0 = <&led_pins>;
62 pinctrl-names = "default";
63
64 power_white: power_white {
65 label = "white:power";
66 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
67 default-state = "keep";
68 };
69
70 power_amber: power_amber {
71 label = "amber:power";
72 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
73 };
74
75 wan_white {
76 label = "white:wan";
77 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
78 };
79
80 wan_amber {
81 label = "amber:wan";
82 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
83 };
84
85 wifi {
86 label = "white:wifi";
87 gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
88 };
89
90 wps {
91 label = "white:wps";
92 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
93 };
94 };
95 };
96
97 &qcom_pinmux {
98 button_pins: button_pins {
99 mux {
100 pins = "gpio6", "gpio54", "gpio65";
101 function = "gpio";
102 drive-strength = <2>;
103 bias-pull-up;
104 };
105 };
106
107 led_pins: led_pins {
108 mux {
109 pins = "gpio7", "gpio8", "gpio9",
110 "gpio22", "gpio23", "gpio24",
111 "gpio26", "gpio53", "gpio64";
112 function = "gpio";
113 drive-strength = <2>;
114 bias-pull-down;
115 };
116 };
117
118 mdio0_pins: mdio0_pins {
119 clk {
120 pins = "gpio1";
121 input-disable;
122 };
123 };
124
125 rgmii2_pins: rgmii2_pins {
126 tx {
127 pins = "gpio27", "gpio28", "gpio29",
128 "gpio30", "gpio31", "gpio32";
129 input-disable;
130 };
131 };
132
133 spi_pins: spi_pins {
134 mux {
135 pins = "gpio18", "gpio19", "gpio21";
136 function = "gsbi5";
137 bias-pull-down;
138 };
139
140 data {
141 pins = "gpio18", "gpio19";
142 drive-strength = <10>;
143 };
144
145 cs {
146 pins = "gpio20";
147 drive-strength = <10>;
148 bias-pull-up;
149 };
150
151 clk {
152 pins = "gpio21";
153 drive-strength = <12>;
154 };
155 };
156
157 spi6_pins: spi6_pins {
158 mux {
159 pins = "gpio55", "gpio56", "gpio58";
160 function = "gsbi6";
161 bias-pull-down;
162 };
163
164 mosi {
165 pins = "gpio55";
166 drive-strength = <12>;
167 };
168
169 miso {
170 pins = "gpio56";
171 drive-strength = <14>;
172 };
173
174 cs {
175 pins = "gpio57";
176 drive-strength = <12>;
177 bias-pull-up;
178 };
179
180 clk {
181 pins = "gpio58";
182 drive-strength = <12>;
183 };
184
185 reset {
186 pins = "gpio33";
187 drive-strength = <10>;
188 bias-pull-down;
189 output-high;
190 };
191 };
192
193 usb0_pwr_en_pins: usb0_pwr_en_pins {
194 mux {
195 pins = "gpio15";
196 function = "gpio";
197 drive-strength = <12>;
198 bias-pull-down;
199 output-high;
200 };
201 };
202
203 usb1_pwr_en_pins: usb1_pwr_en_pins {
204 mux {
205 pins = "gpio16", "gpio68";
206 function = "gpio";
207 drive-strength = <12>;
208 bias-pull-down;
209 output-high;
210 };
211 };
212 };
213
214 &nand_controller {
215 status = "okay";
216
217 pinctrl-0 = <&nand_pins>;
218 pinctrl-names = "default";
219
220 nand@0 {
221 reg = <0>;
222 compatible = "qcom,nandcs";
223
224 nand-ecc-strength = <4>;
225 nand-bus-width = <8>;
226 nand-ecc-step-size = <512>;
227
228 nand-is-boot-medium;
229 qcom,boot_pages_size = <0x1180000>;
230
231 partitions: partitions {
232 compatible = "fixed-partitions";
233 #address-cells = <1>;
234 #size-cells = <1>;
235
236 partition@0 {
237 label = "qcadata";
238 reg = <0x0000000 0x0c80000>;
239 read-only;
240 };
241
242 partition@c80000 {
243 label = "APPSBL";
244 reg = <0x0c80000 0x0500000>;
245 read-only;
246 };
247
248 partition@1180000 {
249 label = "APPSBLENV";
250 reg = <0x1180000 0x0080000>;
251 read-only;
252 };
253
254 art: partition@1200000 {
255 label = "art";
256 reg = <0x1200000 0x0140000>;
257 read-only;
258 compatible = "nvmem-cells";
259 #address-cells = <1>;
260 #size-cells = <1>;
261
262 macaddr_art_0: macaddr@0 {
263 reg = <0x0 0x6>;
264 };
265
266 macaddr_art_6: macaddr@6 {
267 reg = <0x6 0x6>;
268 };
269
270 precal_art_1000: precal@1000 {
271 reg = <0x1000 0x2f20>;
272 };
273
274 precal_art_5000: precal@5000 {
275 reg = <0x5000 0x2f20>;
276 };
277 };
278
279 partition@1340000 {
280 label = "artbak";
281 reg = <0x1340000 0x0140000>;
282 read-only;
283 };
284
285 partition@1480000 {
286 label = "kernel";
287 reg = <0x1480000 0x0400000>;
288 };
289 };
290 };
291 };
292
293 &mdio0 {
294 status = "okay";
295
296 pinctrl-0 = <&mdio0_pins>;
297 pinctrl-names = "default";
298
299 phy0: ethernet-phy@0 {
300 reg = <0>;
301 qca,ar8327-initvals = <
302 0x00004 0x7600000 /* PAD0_MODE */
303 0x00008 0x1000000 /* PAD5_MODE */
304 0x0000c 0x80 /* PAD6_MODE */
305 0x000e4 0xaa545 /* MAC_POWER_SEL */
306 0x000e0 0xc74164de /* SGMII_CTRL */
307 0x0007c 0x4e /* PORT0_STATUS */
308 0x00094 0x4e /* PORT6_STATUS */
309 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
310 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
311 0x00978 0x19008643 /* QM_PORT1_CTRL0 */
312 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
313 0x00980 0x19008643 /* QM_PORT2_CTRL0 */
314 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
315 0x00988 0x19008643 /* QM_PORT3_CTRL0 */
316 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
317 0x00990 0x19008643 /* QM_PORT4_CTRL0 */
318 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
319 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
320 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
321 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
322 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
323 >;
324 qca,ar8327-vlans = <
325 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */
326 0x2 0x21 /* VLAN2 Ports 0/5 */
327 >;
328 };
329
330 phy4: ethernet-phy@4 {
331 reg = <4>;
332 qca,ar8327-initvals = <
333 0x000e4 0x6a545 /* MAC_POWER_SEL */
334 0x0000c 0x80 /* PAD6_MODE */
335 >;
336 };
337 };
338
339 &gmac1 {
340 status = "okay";
341
342 phy-mode = "rgmii";
343 qcom,id = <1>;
344 qcom,phy_mdio_addr = <4>;
345 qcom,poll_required = <0>;
346 qcom,rgmii_delay = <1>;
347 qcom,phy_mii_type = <0>;
348 qcom,emulation = <0>;
349 qcom,irq = <255>;
350 mdiobus = <&mdio0>;
351
352 pinctrl-0 = <&rgmii2_pins>;
353 pinctrl-names = "default";
354
355 nvmem-cells = <&macaddr_art_6>;
356 nvmem-cell-names = "mac-address";
357
358 fixed-link {
359 speed = <1000>;
360 full-duplex;
361 };
362 };
363
364 &gmac2 {
365 status = "okay";
366
367 phy-mode = "sgmii";
368 qcom,id = <2>;
369 qcom,phy_mdio_addr = <0>; /* none */
370 qcom,poll_required = <0>; /* no polling */
371 qcom,rgmii_delay = <0>;
372 qcom,phy_mii_type = <1>;
373 qcom,emulation = <0>;
374 qcom,irq = <258>;
375 mdiobus = <&mdio0>;
376
377 nvmem-cells = <&macaddr_art_0>;
378 nvmem-cell-names = "mac-address";
379
380 fixed-link {
381 speed = <1000>;
382 full-duplex;
383 };
384 };
385
386 &adm_dma {
387 status = "okay";
388 };
389
390 &sata_phy {
391 status = "okay";
392 };
393
394 &sata {
395 status = "okay";
396 };
397
398 &usb3_0 {
399 status = "okay";
400
401 pinctrl-0 = <&usb0_pwr_en_pins>;
402 pinctrl-names = "default";
403 };
404
405 &usb3_1 {
406 status = "okay";
407
408 pinctrl-0 = <&usb1_pwr_en_pins>;
409 pinctrl-names = "default";
410 };
411
412 &pcie0 {
413 status = "okay";
414
415 bridge@0,0 {
416 reg = <0x00000000 0 0 0 0>;
417 #address-cells = <3>;
418 #size-cells = <2>;
419 ranges;
420
421 wifi0: wifi@1,0 {
422 compatible = "pci168c,0046";
423 reg = <0x00010000 0 0 0 0>;
424 };
425 };
426 };
427
428 &pcie1 {
429 status = "okay";
430
431 max-link-speed = <1>;
432
433 bridge@0,0 {
434 reg = <0x00000000 0 0 0 0>;
435 #address-cells = <3>;
436 #size-cells = <2>;
437 ranges;
438
439 wifi1: wifi@1,0 {
440 compatible = "pci168c,0046";
441 reg = <0x00010000 0 0 0 0>;
442 };
443 };
444 };
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