1 // SPDX-License-Identifier: GPL-2.0-or-later
3 #include "qcom-ipq8065.dtsi"
4 #include <dt-bindings/input/input.h>
7 model = "Askey RT4230W REV6";
8 compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
11 reg = <0x42000000 0x3e000000>;
12 device_type = "memory";
17 led-failsafe = &ledctrl1;
18 led-running = &ledctrl2;
19 led-upgrade = &ledctrl3;
23 bootargs = "rootfstype=squashfs noinitrd";
27 compatible = "gpio-keys";
28 pinctrl-0 = <&button_pins>;
29 pinctrl-names = "default";
33 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
34 linux,code = <KEY_RESTART>;
39 gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
40 linux,code = <KEY_WPS_BUTTON>;
45 compatible = "gpio-leds";
46 pinctrl-0 = <&led_pins>;
47 pinctrl-names = "default";
51 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
56 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
61 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
67 button_pins: button_pins {
69 pins = "gpio54", "gpio68";
78 pins = "gpio22", "gpio23", "gpio24";
85 rgmii2_pins: rgmii2_pins {
87 pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
88 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
95 pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
103 drive-strength = <12>;
109 qcom,mode = <GSBI_PROT_SPI>;
115 pinctrl-0 = <&spi_pins>;
116 pinctrl-names = "default";
118 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
121 compatible = "everspin,mr25h256";
122 #address-cells = <1>;
124 spi-max-frequency = <40000000>;
133 pinctrl-0 = <&nand_pins>;
134 pinctrl-names = "default";
138 compatible = "qcom,nandcs";
140 nand-ecc-strength = <4>;
141 nand-bus-width = <8>;
142 nand-ecc-step-size = <512>;
145 compatible = "fixed-partitions";
146 #address-cells = <1>;
151 reg = <0x0000000 0x0040000>;
156 reg = <0x0040000 0x0140000>;
161 reg = <0x0180000 0x0140000>;
166 reg = <0x02c0000 0x0280000>;
170 label = "0:DDRCONFIG";
171 reg = <0x0540000 0x0120000>;
176 reg = <0x0660000 0x0120000>;
181 reg = <0x0780000 0x0280000>;
186 reg = <0x0a00000 0x0280000>;
191 reg = <0x0c80000 0x0500000>;
195 label = "0:APPSBLENV";
196 reg = <0x1180000 0x0080000>;
198 ART: partition@1200000 {
200 reg = <0x1200000 0x0140000>;
204 label = "0:BOOTCONFIG";
205 reg = <0x1340000 0x0060000>;
210 reg = <0x13a0000 0x0140000>;
215 reg = <0x14e0000 0x0280000>;
219 label = "0:DDRCONFIG_1";
220 reg = <0x1760000 0x0120000>;
225 reg = <0x1880000 0x0120000>;
230 reg = <0x19a0000 0x0280000>;
235 reg = <0x1c20000 0x0280000>;
239 label = "0:BOOTCONFIG1";
240 reg = <0x1ea0000 0x0060000>;
244 label = "0:APPSBL_1";
245 reg = <0x1f00000 0x0500000>;
250 reg = <0x2400000 0x1a000000>;
259 pinctrl-0 = <&mdio0_pins>;
260 pinctrl-names = "default";
262 phy0: ethernet-phy@0 {
264 qca,ar8327-initvals = <
265 0x00004 0x7600000 /* PAD0_MODE */
266 0x00008 0x1000000 /* PAD5_MODE */
267 0x0000c 0x80 /* PAD6_MODE */
268 0x000e4 0xaa545 /* MAC_POWER_SEL */
269 0x000e0 0xc74164de /* SGMII_CTRL */
270 0x0007c 0x4e /* PORT0_STATUS */
271 0x00094 0x4e /* PORT6_STATUS */
272 0x00050 0xcf02cf02 /* LED_CTRL_0 */
273 0x00054 0xc832c832 /* LED_CTRL_1 */
283 nvmem-cells = <&macaddr_ART_0>;
284 nvmem-cell-names = "mac-address";
286 pinctrl-0 = <&rgmii2_pins>;
287 pinctrl-names = "default";
300 nvmem-cells = <&macaddr_ART_6>;
301 nvmem-cell-names = "mac-address";
323 reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
324 pinctrl-0 = <&pcie0_pins>;
325 pinctrl-names = "default";
330 reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
331 pinctrl-0 = <&pcie1_pins>;
332 pinctrl-names = "default";
333 max-link-speed = <1>;
337 compatible = "nvmem-cells";
338 #address-cells = <1>;
341 macaddr_ART_0: macaddr@0 {
345 macaddr_ART_6: macaddr@6 {