ipq806x: avoid duplicate partition nodes
[openwrt/staging/jow.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065-tr4400-v2.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "qcom-ipq8065-smb208.dtsi"
4 #include <dt-bindings/input/input.h>
5
6 / {
7 model = "Arris TR4400 v2";
8 compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
9
10 memory@0 {
11 reg = <0x42000000 0x1e000000>;
12 device_type = "memory";
13 };
14
15 aliases {
16 led-boot = &led_status_blue;
17 led-failsafe = &led_status_red;
18 led-running = &led_status_blue;
19 led-upgrade = &led_status_red;
20 };
21
22 chosen {
23 bootargs = "rootfstype=squashfs noinitrd";
24 };
25
26 keys {
27 compatible = "gpio-keys";
28 pinctrl-0 = <&button_pins>;
29 pinctrl-names = "default";
30
31 reset {
32 label = "reset";
33 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
34 linux,code = <KEY_RESTART>;
35 debounce-interval = <60>;
36 wakeup-source;
37 };
38
39 wps {
40 label = "wps";
41 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_WPS_BUTTON>;
43 debounce-interval = <60>;
44 wakeup-source;
45 };
46 };
47
48 leds {
49 compatible = "gpio-leds";
50 pinctrl-0 = <&led_pins>;
51 pinctrl-names = "default";
52
53 led_status_red: status_red {
54 label = "red:status";
55 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
56 };
57
58 led_status_blue: status_blue {
59 label = "blue:status";
60 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
61 };
62 };
63 };
64
65 &qcom_pinmux {
66 button_pins: button_pins {
67 mux {
68 pins = "gpio6", "gpio54";
69 function = "gpio";
70 drive-strength = <2>;
71 bias-pull-up;
72 };
73 };
74
75 led_pins: led_pins {
76 mux {
77 pins = "gpio7", "gpio8";
78 function = "gpio";
79 drive-strength = <2>;
80 bias-pull-down;
81 };
82 };
83
84 rgmii2_pins: rgmii2-pins {
85 tx {
86 pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
87 input-disable;
88 };
89 };
90
91 spi_pins: spi_pins {
92 cs {
93 pins = "gpio20";
94 drive-strength = <12>;
95 };
96 };
97 };
98
99 &gsbi5 {
100 qcom,mode = <GSBI_PROT_SPI>;
101 status = "okay";
102
103 spi@1a280000 {
104 status = "okay";
105
106 pinctrl-0 = <&spi_pins>;
107 pinctrl-names = "default";
108
109 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
110
111 flash@0 {
112 compatible = "everspin,mr25h256";
113 spi-max-frequency = <40000000>;
114 reg = <0>;
115 };
116 };
117 };
118
119 &nand {
120 status = "okay";
121
122 nand@0 {
123 reg = <0>;
124 compatible = "qcom,nandcs";
125
126 nand-ecc-strength = <4>;
127 nand-bus-width = <8>;
128 nand-ecc-step-size = <512>;
129
130 qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
131
132 partitions {
133 compatible = "fixed-partitions";
134 #address-cells = <1>;
135 #size-cells = <1>;
136
137 partition@0 {
138 label = "0:SBL1";
139 reg = <0x0000000 0x0040000>;
140 read-only;
141 };
142 partition@40000 {
143 label = "0:MIBIB";
144 reg = <0x0040000 0x0140000>;
145 read-only;
146 };
147 partition@180000 {
148 label = "0:SBL2";
149 reg = <0x0180000 0x0140000>;
150 read-only;
151 };
152 partition@2c0000 {
153 label = "0:SBL3";
154 reg = <0x02c0000 0x0280000>;
155 read-only;
156 };
157 partition@540000 {
158 label = "0:DDRCONFIG";
159 reg = <0x0540000 0x0120000>;
160 read-only;
161 };
162 partition@660000 {
163 label = "0:SSD";
164 reg = <0x0660000 0x0120000>;
165 read-only;
166 };
167 partition@780000 {
168 label = "0:TZ";
169 reg = <0x0780000 0x0280000>;
170 read-only;
171 };
172 partition@a00000 {
173 label = "0:RPM";
174 reg = <0x0a00000 0x0280000>;
175 read-only;
176 };
177 partition@c80000 {
178 label = "0:APPSBL";
179 reg = <0x0c80000 0x0500000>;
180 read-only;
181 };
182 partition@1180000 {
183 label = "0:APPSBLENV";
184 reg = <0x1180000 0x0080000>;
185 };
186 partition@1200000 {
187 label = "0:ART";
188 reg = <0x1200000 0x0140000>;
189 read-only;
190
191 nvmem-layout {
192 compatible = "fixed-layout";
193 #address-cells = <1>;
194 #size-cells = <1>;
195
196 precal_ART_1000: precal@1000 {
197 reg = <0x1000 0x2f20>;
198 };
199 precal_ART_5000: precal@5000 {
200 reg = <0x5000 0x2f20>;
201 };
202 };
203 };
204 stock_partition@1340000 {
205 label = "stock_rootfs";
206 reg = <0x1340000 0x4000000>;
207
208 compatible = "fixed-partitions";
209 #address-cells = <1>;
210 #size-cells = <1>;
211
212 partition@0 {
213 label = "extra";
214 reg = <0x0 0x4000000>;
215 };
216 };
217 partition@5340000 {
218 label = "0:BOOTCONFIG";
219 reg = <0x5340000 0x0060000>;
220 read-only;
221 };
222 partition@53a0000 {
223 label = "0:SBL2_1";
224 reg = <0x53a0000 0x0140000>;
225 read-only;
226 };
227 partition@54e0000 {
228 label = "0:SBL3_1";
229 reg = <0x54e0000 0x0280000>;
230 read-only;
231 };
232 partition@5760000 {
233 label = "0:DDRCONFIG_1";
234 reg = <0x5760000 0x0120000>;
235 read-only;
236 };
237 partition@5880000 {
238 label = "0:SSD_1";
239 reg = <0x5880000 0x0120000>;
240 read-only;
241 };
242 partition@59a0000 {
243 label = "0:TZ_1";
244 reg = <0x59a0000 0x0280000>;
245 read-only;
246 };
247 partition@5c20000 {
248 label = "0:RPM_1";
249 reg = <0x5c20000 0x0280000>;
250 read-only;
251 };
252 partition@5ea0000 {
253 label = "0:BOOTCONFIG1";
254 reg = <0x5ea0000 0x0060000>;
255 read-only;
256 };
257 partition@5f00000 {
258 label = "0:APPSBL_1";
259 reg = <0x5f00000 0x0500000>;
260 read-only;
261 };
262 stock_partition@6400000 {
263 label = "stock_rootfs_1";
264 reg = <0x6400000 0x4000000>;
265
266 compatible = "fixed-partitions";
267 #address-cells = <1>;
268 #size-cells = <1>;
269
270 partition@0 {
271 label = "fw_env";
272 reg = <0x0 0x100000>;
273
274 nvmem-layout {
275 compatible = "fixed-layout";
276 #address-cells = <1>;
277 #size-cells = <1>;
278
279 macaddr_fw_env_0: macaddr@0 {
280 reg = <0x00 0x6>;
281 };
282 macaddr_fw_env_6: macaddr@6 {
283 reg = <0x06 0x6>;
284 };
285 macaddr_fw_env_c: macaddr@c {
286 reg = <0x0c 0x6>;
287 };
288 macaddr_fw_env_12: macaddr@12 {
289 reg = <0x12 0x6>;
290 };
291 macaddr_fw_env_18: macaddr@18 {
292 reg = <0x18 0x6>;
293 };
294 };
295 };
296
297 partition@100000 {
298 label = "ubi";
299 reg = <0x100000 0x9b00000>;
300 };
301 };
302 stock_partition@a400000 {
303 label = "stock_fw_env";
304 reg = <0xa400000 0x0100000>;
305 };
306 stock_partition@a500000 {
307 label = "stock_config";
308 reg = <0xa500000 0x0800000>;
309 };
310 stock_partition@ad00000 {
311 label = "stock_PKI";
312 reg = <0xad00000 0x0200000>;
313 };
314 stock_partition@af00000 {
315 label = "stock_scfgmgr";
316 reg = <0xaf00000 0x0100000>;
317 };
318 };
319 };
320 };
321
322 &mdio0 {
323 status = "okay";
324
325 pinctrl-0 = <&mdio0_pins>;
326 pinctrl-names = "default";
327
328 switch@10 {
329 compatible = "qca,qca8337";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 reg = <0x10>;
333
334 ports {
335 #address-cells = <1>;
336 #size-cells = <0>;
337
338 port@0 {
339 reg = <0>;
340 label = "cpu";
341 ethernet = <&gmac0>;
342 phy-mode = "rgmii";
343 tx-internal-delay-ps = <1000>;
344 rx-internal-delay-ps = <1000>;
345
346 fixed-link {
347 speed = <1000>;
348 full-duplex;
349 };
350 };
351
352 port@1 {
353 reg = <1>;
354 label = "lan1";
355 phy-mode = "internal";
356 phy-handle = <&phy_port1>;
357 };
358
359 port@2 {
360 reg = <2>;
361 label = "lan2";
362 phy-mode = "internal";
363 phy-handle = <&phy_port2>;
364 };
365
366 port@3 {
367 reg = <3>;
368 label = "lan3";
369 phy-mode = "internal";
370 phy-handle = <&phy_port3>;
371 };
372
373 port@4 {
374 reg = <4>;
375 label = "lan4";
376 phy-mode = "internal";
377 phy-handle = <&phy_port4>;
378 };
379
380 port@6 {
381 reg = <6>;
382 label = "cpu";
383 ethernet = <&gmac1>;
384 phy-mode = "sgmii";
385 qca,sgmii-enable-pll;
386
387 fixed-link {
388 speed = <1000>;
389 full-duplex;
390 };
391 };
392 };
393
394 mdio {
395 #address-cells = <1>;
396 #size-cells = <0>;
397
398 phy_port1: phy@0 {
399 reg = <0>;
400 };
401
402 phy_port2: phy@1 {
403 reg = <1>;
404 };
405
406 phy_port3: phy@2 {
407 reg = <2>;
408 };
409
410 phy_port4: phy@3 {
411 reg = <3>;
412 };
413 };
414 };
415
416 phy7: ethernet-phy@7 {
417 reg = <7>;
418 };
419 };
420
421 &gmac0 {
422 status = "okay";
423 phy-mode = "rgmii";
424 qcom,id = <0>;
425
426 nvmem-cells = <&macaddr_fw_env_18>;
427 nvmem-cell-names = "mac-address";
428
429 pinctrl-0 = <&rgmii2_pins>;
430 pinctrl-names = "default";
431
432 fixed-link {
433 speed = <1000>;
434 full-duplex;
435 };
436 };
437
438 &gmac1 {
439 status = "okay";
440 phy-mode = "sgmii";
441 qcom,id = <1>;
442
443 nvmem-cells = <&macaddr_fw_env_0>;
444 nvmem-cell-names = "mac-address";
445
446 fixed-link {
447 speed = <1000>;
448 full-duplex;
449 };
450 };
451
452 &gmac3 {
453 status = "okay";
454 phy-mode = "sgmii";
455 qcom,id = <3>;
456 phy-handle = <&phy7>;
457
458 nvmem-cells = <&macaddr_fw_env_6>;
459 nvmem-cell-names = "mac-address";
460 };
461
462 &adm_dma {
463 status = "okay";
464 };
465
466 &hs_phy_1 {
467 status = "okay";
468 };
469
470 &ss_phy_1 {
471 status = "okay";
472 };
473
474 &usb3_1 {
475 status = "okay";
476 };
477
478 &pcie0 {
479 status = "okay";
480 reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
481 pinctrl-0 = <&pcie0_pins>;
482 pinctrl-names = "default";
483
484 bridge@0,0 {
485 reg = <0x00000000 0 0 0 0>;
486 #address-cells = <3>;
487 #size-cells = <2>;
488 ranges;
489
490 wifi0: wifi@1,0 {
491 compatible = "pci168c,0046";
492 reg = <0x00010000 0 0 0 0>;
493
494 nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
495 nvmem-cell-names = "pre-calibration", "mac-address";
496 };
497 };
498 };
499
500 &pcie1 {
501 status = "okay";
502 reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
503 pinctrl-0 = <&pcie1_pins>;
504 pinctrl-names = "default";
505 max-link-speed = <1>;
506
507 bridge@0,0 {
508 reg = <0x00000000 0 0 0 0>;
509 #address-cells = <3>;
510 #size-cells = <2>;
511 ranges;
512
513 wifi1: wifi@1,0 {
514 compatible = "pci168c,0040";
515 reg = <0x00010000 0 0 0 0>;
516
517 nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
518 nvmem-cell-names = "pre-calibration", "mac-address";
519 };
520 };
521 };