3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
6 #include <dt-bindings/mfd/qcom-rpm.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Qualcomm IPQ8065";
15 compatible = "qcom,ipq8065", "qcom,ipq8064";
16 interrupt-parent = <&intc>;
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
27 next-level-cache = <&L2>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 qcom,imem = <&qfprom>;
33 clock-latency = <100000>;
34 cpu-supply = <&smb208_s2a>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
39 cpu-idle-states = <&CPU_SPC>;
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
47 next-level-cache = <&L2>;
50 clocks = <&kraitcc 1>, <&kraitcc 4>;
51 clock-names = "cpu", "l2";
52 qcom,imem = <&qfprom>;
53 clock-latency = <100000>;
54 cpu-supply = <&smb208_s2b>;
55 cooling-min-state = <0>;
56 cooling-max-state = <10>;
58 cpu-idle-states = <&CPU_SPC>;
68 qcom,l2-rates = <384000000 1000000000 1200000000>;
73 compatible = "qcom,idle-state-spc",
75 entry-latency-us = <400>;
76 exit-latency-us = <900>;
77 min-residency-us = <3000>;
84 polling-delay-passive = <250>;
85 polling-delay = <1000>;
87 thermal-sensors = <&gcc 5>;
88 coefficients = <1132 0>;
92 temperature = <75000>;
97 temperature = <110000>;
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
108 thermal-sensors = <&gcc 6>;
109 coefficients = <1132 0>;
113 temperature = <75000>;
118 temperature = <110000>;
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
129 thermal-sensors = <&gcc 7>;
130 coefficients = <1199 0>;
134 temperature = <75000>;
139 temperature = <110000>;
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
150 thermal-sensors = <&gcc 8>;
151 coefficients = <1132 0>;
155 temperature = <75000>;
160 temperature = <110000>;
169 compatible = "qcom,krait-pmu";
170 interrupts = <1 10 0x304>;
174 #address-cells = <1>;
179 reg = <0x40000000 0x1000000>;
183 smem: smem@41000000 {
184 reg = <0x41000000 0x200000>;
192 compatible = "fixed-clock";
194 clock-frequency = <25000000>;
198 compatible = "fixed-clock";
200 clock-frequency = <25000000>;
203 sleep_clk: sleep_clk {
204 compatible = "fixed-clock";
205 clock-frequency = <32768>;
210 kraitcc: clock-controller {
211 compatible = "qcom,krait-cc-v1";
217 qcom,speed0-pvs0-bin-v0 =
218 < 1725000000 1262500 >,
219 < 1400000000 1175000 >,
220 < 1000000000 1100000 >,
221 < 800000000 1050000 >,
222 < 600000000 1000000 >,
223 < 384000000 975000 >;
224 qcom,speed0-pvs1-bin-v0 =
225 < 1725000000 1225000 >,
226 < 1400000000 1150000 >,
227 < 1000000000 1075000 >,
228 < 800000000 1025000 >,
229 < 600000000 975000 >,
230 < 384000000 950000 >;
231 qcom,speed0-pvs2-bin-v0 =
232 < 1725000000 1200000 >,
233 < 1400000000 1125000 >,
234 < 1000000000 1050000 >,
235 < 800000000 1000000 >,
236 < 600000000 950000 >,
237 < 384000000 925000 >;
238 qcom,speed0-pvs3-bin-v0 =
239 < 1725000000 1175000 >,
240 < 1400000000 1100000 >,
241 < 1000000000 1025000 >,
242 < 800000000 975000 >,
243 < 600000000 925000 >,
244 < 384000000 900000 >;
245 qcom,speed0-pvs4-bin-v0 =
246 < 1725000000 1150000 >,
247 < 1400000000 1075000 >,
248 < 1000000000 1000000 >,
249 < 800000000 950000 >,
250 < 600000000 900000 >,
251 < 384000000 875000 >;
252 qcom,speed0-pvs5-bin-v0 =
253 < 1725000000 1100000 >,
254 < 1400000000 1025000 >,
255 < 1000000000 950000 >,
256 < 800000000 900000 >,
257 < 600000000 850000 >,
258 < 384000000 825000 >;
259 qcom,speed0-pvs6-bin-v0 =
260 < 1725000000 1050000 >,
261 < 1400000000 975000 >,
262 < 1000000000 900000 >,
263 < 800000000 850000 >,
264 < 600000000 800000 >,
265 < 384000000 775000 >;
269 #address-cells = <1>;
272 compatible = "simple-bus";
275 compatible = "qcom,lpass-cpu";
277 clocks = <&lcc AHBIX_CLK>,
280 clock-names = "ahbix-clk",
283 interrupts = <0 85 1>;
284 interrupt-names = "lpass-irq-lpaif";
285 reg = <0x28100000 0x10000>;
286 reg-names = "lpass-lpaif";
289 qfprom: qfprom@700000 {
290 compatible = "qcom,qfprom", "syscon";
291 reg = <0x00700000 0x1000>;
292 #address-cells = <1>;
299 tsens_backup: backup_calib {
305 compatible = "qcom,rpm-ipq8064";
306 reg = <0x108000 0x1000>;
307 qcom,ipc = <&l2cc 0x8 2>;
309 interrupts = <0 19 0>,
312 interrupt-names = "ack",
316 #address-cells = <1>;
319 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
322 rpmcc: clock-controller {
323 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
328 compatible = "qcom,rpm-smb208-regulators";
331 regulator-min-microvolt = <1050000>;
332 regulator-max-microvolt = <1150000>;
333 qcom,switch-mode-frequency = <1200000>;
337 regulator-min-microvolt = <1050000>;
338 regulator-max-microvolt = <1150000>;
339 qcom,switch-mode-frequency = <1200000>;
343 regulator-min-microvolt = <775000>;
344 regulator-max-microvolt = <1275000>;
345 qcom,switch-mode-frequency = <1200000>;
349 regulator-min-microvolt = <775000>;
350 regulator-max-microvolt = <1275000>;
351 qcom,switch-mode-frequency = <1200000>;
357 compatible = "qcom,prng";
358 reg = <0x1a500000 0x200>;
359 clocks = <&gcc PRNG_CLK>;
360 clock-names = "core";
363 qcom,msm-imem@2A03F000 {
364 compatible = "qcom,msm-imem";
365 reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
366 ranges = <0x0 0x2A03F000 0x1000>;
367 #address-cells = <1>;
371 compatible = "qcom,msm-imem-download_mode";
376 compatible = "qcom,msm-imem-restart_reason";
381 compatible = "qcom,msm-imem-l2_dump_offset";
386 qcom_pinmux: pinmux@800000 {
387 compatible = "qcom,ipq8064-pinctrl";
388 reg = <0x800000 0x4000>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 interrupts = <0 16 0x4>;
396 pcie0_pins: pcie0_pinmux {
399 function = "pcie1_rst";
400 drive-strength = <2>;
405 pcie1_pins: pcie1_pinmux {
408 function = "pcie2_rst";
409 drive-strength = <2>;
414 pcie2_pins: pcie2_pinmux {
417 function = "pcie3_rst";
418 drive-strength = <2>;
425 intc: interrupt-controller@2000000 {
426 compatible = "qcom,msm-qgic2";
427 interrupt-controller;
428 #interrupt-cells = <3>;
429 reg = <0x02000000 0x1000>,
434 compatible = "qcom,kpss-timer", "qcom,msm-timer";
435 interrupts = <1 1 0x301>,
440 reg = <0x0200a000 0x100>;
441 clock-frequency = <25000000>,
443 clocks = <&sleep_clk>;
444 clock-names = "sleep";
445 cpu-offset = <0x80000>;
448 acc0: clock-controller@2088000 {
449 compatible = "qcom,kpss-acc-v1";
450 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
451 clock-output-names = "acpu0_aux";
454 acc1: clock-controller@2098000 {
455 compatible = "qcom,kpss-acc-v1";
456 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
457 clock-output-names = "acpu1_aux";
460 l2cc: clock-controller@2011000 {
461 compatible = "qcom,kpss-gcc", "syscon";
462 reg = <0x2011000 0x1000>;
463 clock-output-names = "acpu_l2_aux";
466 saw0: regulator@2089000 {
467 compatible = "qcom,saw2", "syscon";
468 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
472 saw1: regulator@2099000 {
473 compatible = "qcom,saw2", "syscon";
474 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
478 saw_l2: regulator@02012000 {
479 compatible = "qcom,saw2", "syscon";
480 reg = <0x02012000 0x1000>;
484 sic_non_secure: sic-non-secure@12100000 {
485 compatible = "syscon";
486 reg = <0x12100000 0x10000>;
489 gsbi1: gsbi@12440000 {
490 compatible = "qcom,gsbi-v1.0.0";
492 reg = <0x12440000 0x100>;
493 clocks = <&gcc GSBI1_H_CLK>;
494 clock-names = "iface";
495 #address-cells = <1>;
500 syscon-tcsr = <&tcsr>;
502 uart1: serial@12450000 {
503 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
504 reg = <0x12450000 0x1000>,
506 interrupts = <0 193 0x0>;
507 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
508 clock-names = "core", "iface";
513 compatible = "qcom,i2c-qup-v1.1.1";
514 reg = <0x12460000 0x1000>;
515 interrupts = <0 194 0>;
517 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
518 clock-names = "core", "iface";
521 #address-cells = <1>;
527 gsbi2: gsbi@12480000 {
528 compatible = "qcom,gsbi-v1.0.0";
530 reg = <0x12480000 0x100>;
531 clocks = <&gcc GSBI2_H_CLK>;
532 clock-names = "iface";
533 #address-cells = <1>;
538 syscon-tcsr = <&tcsr>;
540 uart2: serial@12490000 {
541 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
542 reg = <0x12490000 0x1000>,
544 interrupts = <0 195 0x0>;
545 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
546 clock-names = "core", "iface";
551 compatible = "qcom,i2c-qup-v1.1.1";
552 reg = <0x124a0000 0x1000>;
553 interrupts = <0 196 0>;
555 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
556 clock-names = "core", "iface";
559 #address-cells = <1>;
565 gsbi4: gsbi@16300000 {
566 compatible = "qcom,gsbi-v1.0.0";
568 reg = <0x16300000 0x100>;
569 clocks = <&gcc GSBI4_H_CLK>;
570 clock-names = "iface";
571 #address-cells = <1>;
576 syscon-tcsr = <&tcsr>;
578 uart4: serial@16340000 {
579 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
580 reg = <0x16340000 0x1000>,
582 interrupts = <0 152 0x0>;
583 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
584 clock-names = "core", "iface";
589 compatible = "qcom,i2c-qup-v1.1.1";
590 reg = <0x16380000 0x1000>;
591 interrupts = <0 153 0>;
593 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
594 clock-names = "core", "iface";
597 #address-cells = <1>;
602 gsbi5: gsbi@1a200000 {
603 compatible = "qcom,gsbi-v1.0.0";
605 reg = <0x1a200000 0x100>;
606 clocks = <&gcc GSBI5_H_CLK>;
607 clock-names = "iface";
608 #address-cells = <1>;
613 syscon-tcsr = <&tcsr>;
615 uart5: serial@1a240000 {
616 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
617 reg = <0x1a240000 0x1000>,
619 interrupts = <0 154 0x0>;
620 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
621 clock-names = "core", "iface";
626 compatible = "qcom,i2c-qup-v1.1.1";
627 reg = <0x1a280000 0x1000>;
628 interrupts = <0 155 0>;
630 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
631 clock-names = "core", "iface";
634 #address-cells = <1>;
639 compatible = "qcom,spi-qup-v1.1.1";
640 reg = <0x1a280000 0x1000>;
641 interrupts = <0 155 0>;
643 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
644 clock-names = "core", "iface";
647 #address-cells = <1>;
652 gsbi6: gsbi@16500000 {
653 compatible = "qcom,gsbi-v1.0.0";
655 reg = <0x16500000 0x100>;
656 clocks = <&gcc GSBI6_H_CLK>;
657 clock-names = "iface";
658 #address-cells = <1>;
663 syscon-tcsr = <&tcsr>;
665 uart6: serial@16540000 {
666 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
667 reg = <0x16540000 0x1000>,
669 interrupts = <0 156 0x0>;
670 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
671 clock-names = "core", "iface";
676 compatible = "qcom,i2c-qup-v1.1.1";
677 reg = <0x16580000 0x1000>;
678 interrupts = <0 157 0>;
680 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
681 clock-names = "core", "iface";
684 #address-cells = <1>;
689 compatible = "qcom,spi-qup-v1.1.1";
690 reg = <0x16580000 0x1000>;
691 interrupts = <0 157 0>;
693 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
694 clock-names = "core", "iface";
697 #address-cells = <1>;
702 gsbi7: gsbi@16600000 {
703 compatible = "qcom,gsbi-v1.0.0";
705 reg = <0x16600000 0x100>;
706 clocks = <&gcc GSBI7_H_CLK>;
707 clock-names = "iface";
708 #address-cells = <1>;
713 syscon-tcsr = <&tcsr>;
715 uart7: serial@16640000 {
716 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
717 reg = <0x16640000 0x1000>,
719 interrupts = <0 158 0x0>;
720 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
721 clock-names = "core", "iface";
726 compatible = "qcom,i2c-qup-v1.1.1";
727 reg = <0x16680000 0x1000>;
728 interrupts = <0 159 0>;
730 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
731 clock-names = "core", "iface";
734 #address-cells = <1>;
740 sata_phy: sata-phy@1b400000 {
741 compatible = "qcom,ipq806x-sata-phy";
742 reg = <0x1b400000 0x200>;
744 clocks = <&gcc SATA_PHY_CFG_CLK>;
752 compatible = "qcom,ipq806x-ahci", "generic-ahci";
753 reg = <0x29000000 0x180>;
755 interrupts = <0 209 0x0>;
757 clocks = <&gcc SFAB_SATA_S_H_CLK>,
760 <&gcc SATA_RXOOB_CLK>,
761 <&gcc SATA_PMALIVE_CLK>;
762 clock-names = "slave_face", "iface", "core",
765 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
766 assigned-clock-rates = <100000000>, <100000000>;
769 phy-names = "sata-phy";
774 compatible = "qcom,ssbi";
775 reg = <0x00500000 0x1000>;
776 qcom,controller-type = "pmic-arbiter";
779 gcc: clock-controller@900000 {
780 compatible = "qcom,gcc-ipq8064";
781 reg = <0x00900000 0x4000>;
782 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
783 nvmem-cell-names = "calib", "calib_backup";
786 #power-domain-cells = <1>;
787 #thermal-sensor-cells = <1>;
790 lcc: clock-controller@28000000 {
791 compatible = "qcom,lcc-ipq8064";
792 reg = <0x28000000 0x1000>;
797 tcsr: syscon@1a400000 {
798 compatible = "qcom,tcsr-ipq8064", "syscon";
799 reg = <0x1a400000 0x100>;
803 compatible = "qcom,msm-thermal";
804 qcom,sensor-id = <0>;
805 qcom,poll-ms = <250>;
806 qcom,limit-temp = <105>;
807 qcom,temp-hysteresis = <10>;
808 qcom,freq-step = <2>;
809 qcom,core-limit-temp = <115>;
810 qcom,core-temp-hysteresis = <10>;
811 qcom,core-control-mask = <0xe>;
814 sfpb_mutex_block: syscon@1200600 {
815 compatible = "syscon";
816 reg = <0x01200600 0x100>;
819 hs_phy_1: phy@100f8800 {
820 compatible = "qcom,dwc3-hs-usb-phy";
821 reg = <0x100f8800 0x30>;
822 clocks = <&gcc USB30_1_UTMI_CLK>;
829 ss_phy_1: phy@100f8830 {
830 compatible = "qcom,dwc3-ss-usb-phy";
831 reg = <0x100f8830 0x30>;
832 clocks = <&gcc USB30_1_MASTER_CLK>;
839 hs_phy_0: phy@110f8800 {
840 compatible = "qcom,dwc3-hs-usb-phy";
841 reg = <0x110f8800 0x30>;
842 clocks = <&gcc USB30_0_UTMI_CLK>;
849 ss_phy_0: phy@110f8830 {
850 compatible = "qcom,dwc3-ss-usb-phy";
851 reg = <0x110f8830 0x30>;
852 clocks = <&gcc USB30_0_MASTER_CLK>;
860 compatible = "qcom,dwc3";
861 #address-cells = <1>;
863 clocks = <&gcc USB30_0_MASTER_CLK>;
864 clock-names = "core";
866 syscon-tcsr = <&tcsr 0xb0 1>;
871 resets = <&gcc USB30_0_MASTER_RESET>;
872 reset-names = "usb30_mstr_rst";
875 compatible = "snps,dwc3";
876 reg = <0x11000000 0xcd00>;
877 interrupts = <0 110 0x4>;
878 phys = <&hs_phy_0>, <&ss_phy_0>;
879 phy-names = "usb2-phy", "usb3-phy";
881 snps,dis_u3_susphy_quirk;
886 compatible = "qcom,dwc3";
887 #address-cells = <1>;
889 clocks = <&gcc USB30_1_MASTER_CLK>;
890 clock-names = "core";
892 syscon-tcsr = <&tcsr 0xb0 0>;
899 compatible = "snps,dwc3";
900 reg = <0x10000000 0xcd00>;
901 interrupts = <0 205 0x4>;
902 phys = <&hs_phy_1>, <&ss_phy_1>;
903 phy-names = "usb2-phy", "usb3-phy";
905 snps,dis_u3_susphy_quirk;
909 pcie0: pci@1b500000 {
910 compatible = "qcom,pcie-v0";
911 reg = <0x1b500000 0x1000
914 0x0ff00000 0x100000>;
915 reg-names = "dbi", "elbi", "parf", "config";
917 linux,pci-domain = <0>;
918 bus-range = <0x00 0xff>;
920 #address-cells = <3>;
923 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
924 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
926 interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
927 interrupt-names = "msi";
928 #interrupt-cells = <1>;
929 interrupt-map-mask = <0 0 0 0x7>;
930 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
931 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
932 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
933 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
935 clocks = <&gcc PCIE_A_CLK>,
939 <&gcc PCIE_ALT_REF_CLK>;
940 clock-names = "core", "iface", "phy", "aux", "ref";
942 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
943 assigned-clock-rates = <100000000>;
945 resets = <&gcc PCIE_ACLK_RESET>,
946 <&gcc PCIE_HCLK_RESET>,
947 <&gcc PCIE_POR_RESET>,
948 <&gcc PCIE_PCI_RESET>,
949 <&gcc PCIE_PHY_RESET>,
950 <&gcc PCIE_EXT_RESET>;
951 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
953 pinctrl-0 = <&pcie0_pins>;
954 pinctrl-names = "default";
956 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
961 pcie1: pci@1b700000 {
962 compatible = "qcom,pcie-v0";
963 reg = <0x1b700000 0x1000
966 0x31f00000 0x100000>;
967 reg-names = "dbi", "elbi", "parf", "config";
969 linux,pci-domain = <1>;
970 bus-range = <0x00 0xff>;
972 #address-cells = <3>;
975 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
976 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
978 interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
979 interrupt-names = "msi";
980 #interrupt-cells = <1>;
981 interrupt-map-mask = <0 0 0 0x7>;
982 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
983 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
984 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
985 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
987 clocks = <&gcc PCIE_1_A_CLK>,
989 <&gcc PCIE_1_PHY_CLK>,
990 <&gcc PCIE_1_AUX_CLK>,
991 <&gcc PCIE_1_ALT_REF_CLK>;
992 clock-names = "core", "iface", "phy", "aux", "ref";
994 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
995 assigned-clock-rates = <100000000>;
997 resets = <&gcc PCIE_1_ACLK_RESET>,
998 <&gcc PCIE_1_HCLK_RESET>,
999 <&gcc PCIE_1_POR_RESET>,
1000 <&gcc PCIE_1_PCI_RESET>,
1001 <&gcc PCIE_1_PHY_RESET>,
1002 <&gcc PCIE_1_EXT_RESET>;
1003 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1005 pinctrl-0 = <&pcie1_pins>;
1006 pinctrl-names = "default";
1008 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1010 status = "disabled";
1013 pcie2: pci@1b900000 {
1014 compatible = "qcom,pcie-v0";
1015 reg = <0x1b900000 0x1000
1018 0x35f00000 0x100000>;
1019 reg-names = "dbi", "elbi", "parf", "config";
1020 device_type = "pci";
1021 linux,pci-domain = <2>;
1022 bus-range = <0x00 0xff>;
1024 #address-cells = <3>;
1027 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1028 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1030 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
1031 interrupt-names = "msi";
1032 #interrupt-cells = <1>;
1033 interrupt-map-mask = <0 0 0 0x7>;
1034 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1035 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1036 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1037 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1039 clocks = <&gcc PCIE_2_A_CLK>,
1040 <&gcc PCIE_2_H_CLK>,
1041 <&gcc PCIE_2_PHY_CLK>,
1042 <&gcc PCIE_2_AUX_CLK>,
1043 <&gcc PCIE_2_ALT_REF_CLK>;
1044 clock-names = "core", "iface", "phy", "aux", "ref";
1046 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1047 assigned-clock-rates = <100000000>;
1049 resets = <&gcc PCIE_2_ACLK_RESET>,
1050 <&gcc PCIE_2_HCLK_RESET>,
1051 <&gcc PCIE_2_POR_RESET>,
1052 <&gcc PCIE_2_PCI_RESET>,
1053 <&gcc PCIE_2_PHY_RESET>,
1054 <&gcc PCIE_2_EXT_RESET>;
1055 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1057 pinctrl-0 = <&pcie2_pins>;
1058 pinctrl-names = "default";
1060 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1062 status = "disabled";
1065 adm_dma: dma@18300000 {
1066 compatible = "qcom,adm";
1067 reg = <0x18300000 0x100000>;
1068 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
1071 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1072 clock-names = "core", "iface";
1074 resets = <&gcc ADM0_RESET>,
1075 <&gcc ADM0_PBUS_RESET>,
1076 <&gcc ADM0_C0_RESET>,
1077 <&gcc ADM0_C1_RESET>,
1078 <&gcc ADM0_C2_RESET>;
1079 reset-names = "clk", "pbus", "c0", "c1", "c2";
1082 status = "disabled";
1086 compatible = "qcom,ebi2-nandc";
1087 reg = <0x1ac00000 0x800>;
1089 clocks = <&gcc EBI2_CLK>,
1090 <&gcc EBI2_AON_CLK>;
1091 clock-names = "core", "aon";
1093 dmas = <&adm_dma 3>;
1095 qcom,cmd-crci = <15>;
1096 qcom,data-crci = <3>;
1098 status = "disabled";
1101 nss_common: syscon@03000000 {
1102 compatible = "syscon";
1103 reg = <0x03000000 0x0000FFFF>;
1106 qsgmii_csr: syscon@1bb00000 {
1107 compatible = "syscon";
1108 reg = <0x1bb00000 0x000001FF>;
1111 gmac0: ethernet@37000000 {
1112 device_type = "network";
1113 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1114 reg = <0x37000000 0x200000>;
1115 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1116 interrupt-names = "macirq";
1118 qcom,nss-common = <&nss_common>;
1119 qcom,qsgmii-csr = <&qsgmii_csr>;
1121 clocks = <&gcc GMAC_CORE1_CLK>;
1122 clock-names = "stmmaceth";
1124 resets = <&gcc GMAC_CORE1_RESET>;
1125 reset-names = "stmmaceth";
1127 status = "disabled";
1130 gmac1: ethernet@37200000 {
1131 device_type = "network";
1132 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1133 reg = <0x37200000 0x200000>;
1134 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "macirq";
1137 qcom,nss-common = <&nss_common>;
1138 qcom,qsgmii-csr = <&qsgmii_csr>;
1140 clocks = <&gcc GMAC_CORE2_CLK>;
1141 clock-names = "stmmaceth";
1143 resets = <&gcc GMAC_CORE2_RESET>;
1144 reset-names = "stmmaceth";
1146 status = "disabled";
1149 gmac2: ethernet@37400000 {
1150 device_type = "network";
1151 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1152 reg = <0x37400000 0x200000>;
1153 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1154 interrupt-names = "macirq";
1156 qcom,nss-common = <&nss_common>;
1157 qcom,qsgmii-csr = <&qsgmii_csr>;
1159 clocks = <&gcc GMAC_CORE3_CLK>;
1160 clock-names = "stmmaceth";
1162 resets = <&gcc GMAC_CORE3_RESET>;
1163 reset-names = "stmmaceth";
1165 status = "disabled";
1168 gmac3: ethernet@37600000 {
1169 device_type = "network";
1170 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1171 reg = <0x37600000 0x200000>;
1172 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1173 interrupt-names = "macirq";
1175 qcom,nss-common = <&nss_common>;
1176 qcom,qsgmii-csr = <&qsgmii_csr>;
1178 clocks = <&gcc GMAC_CORE4_CLK>;
1179 clock-names = "stmmaceth";
1181 resets = <&gcc GMAC_CORE4_RESET>;
1182 reset-names = "stmmaceth";
1184 status = "disabled";
1187 /* Temporary fixed regulator */
1188 vsdcc_fixed: vsdcc-regulator {
1189 compatible = "regulator-fixed";
1190 regulator-name = "SDCC Power";
1191 regulator-min-microvolt = <3300000>;
1192 regulator-max-microvolt = <3300000>;
1193 regulator-always-on;
1196 sdcc1bam:dma@12402000 {
1197 compatible = "qcom,bam-v1.3.0";
1198 reg = <0x12402000 0x8000>;
1199 interrupts = <0 98 0>;
1200 clocks = <&gcc SDC1_H_CLK>;
1201 clock-names = "bam_clk";
1206 sdcc3bam:dma@12182000 {
1207 compatible = "qcom,bam-v1.3.0";
1208 reg = <0x12182000 0x8000>;
1209 interrupts = <0 96 0>;
1210 clocks = <&gcc SDC3_H_CLK>;
1211 clock-names = "bam_clk";
1217 compatible = "arm,amba-bus";
1218 #address-cells = <1>;
1221 sdcc1: sdcc@12400000 {
1222 status = "disabled";
1223 compatible = "arm,pl18x", "arm,primecell";
1224 arm,primecell-periphid = <0x00051180>;
1225 reg = <0x12400000 0x2000>;
1226 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1227 interrupt-names = "cmd_irq";
1228 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1229 clock-names = "mclk", "apb_pclk";
1231 max-frequency = <96000000>;
1236 vmmc-supply = <&vsdcc_fixed>;
1237 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1238 dma-names = "tx", "rx";
1241 sdcc3: sdcc@12180000 {
1242 compatible = "arm,pl18x", "arm,primecell";
1243 arm,primecell-periphid = <0x00051180>;
1244 status = "disabled";
1245 reg = <0x12180000 0x2000>;
1246 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1247 interrupt-names = "cmd_irq";
1248 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1249 clock-names = "mclk", "apb_pclk";
1253 max-frequency = <192000000>;
1257 vqmmc-supply = <&vsdcc_fixed>;
1258 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1259 dma-names = "tx", "rx";
1264 sfpb_mutex: sfpb-mutex {
1265 compatible = "qcom,sfpb-mutex";
1266 syscon = <&sfpb_mutex_block 4 4>;
1268 #hwlock-cells = <1>;
1272 compatible = "qcom,smem";
1273 memory-region = <&smem>;
1274 hwlocks = <&sfpb_mutex 3>;