3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
6 #include <dt-bindings/mfd/qcom-rpm.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Qualcomm IPQ8065";
15 compatible = "qcom,ipq8065", "qcom,ipq8064";
16 interrupt-parent = <&intc>;
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
27 next-level-cache = <&L2>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
33 clock-latency = <100000>;
34 cpu-supply = <&smb208_s2a>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
46 next-level-cache = <&L2>;
49 clocks = <&kraitcc 1>, <&kraitcc 4>;
50 clock-names = "cpu", "l2";
52 clock-latency = <100000>;
53 cpu-supply = <&smb208_s2b>;
54 cooling-min-state = <0>;
55 cooling-max-state = <10>;
66 qcom,l2-rates = <384000000 1000000000 1200000000>;
71 compatible = "qcom,krait-pmu";
72 interrupts = <1 10 0x304>;
81 reg = <0x40000000 0x1000000>;
86 reg = <0x41000000 0x200000>;
92 sleep_clk: sleep_clk {
93 compatible = "fixed-clock";
94 clock-frequency = <32768>;
99 kraitcc: clock-controller {
100 compatible = "qcom,krait-cc-v1";
106 qcom,speed0-pvs0-bin-v0 =
107 < 1725000000 1262500 >,
108 < 1400000000 1175000 >,
109 < 1000000000 1100000 >,
110 < 800000000 1050000 >,
111 < 600000000 1000000 >,
112 < 384000000 975000 >;
113 qcom,speed0-pvs1-bin-v0 =
114 < 1725000000 1262500 >,
115 < 1400000000 1175000 >,
116 < 1000000000 1100000 >,
117 < 800000000 1050000 >,
118 < 600000000 1000000 >,
119 < 384000000 950000 >;
120 qcom,speed0-pvs2-bin-v0 =
121 < 1725000000 1200000 >,
122 < 1400000000 1125000 >,
123 < 1000000000 1050000 >,
124 < 800000000 1000000 >,
125 < 600000000 950000 >,
126 < 384000000 925000 >;
127 qcom,speed0-pvs3-bin-v0 =
128 < 1725000000 1175000 >,
129 < 1400000000 1100000 >,
130 < 1000000000 1025000 >,
131 < 800000000 975000 >,
132 < 600000000 925000 >,
133 < 384000000 900000 >;
134 qcom,speed0-pvs4-bin-v0 =
135 < 1725000000 1150000 >,
136 < 1400000000 1075000 >,
137 < 1000000000 1000000 >,
138 < 800000000 950000 >,
139 < 600000000 900000 >,
140 < 384000000 875000 >;
141 qcom,speed0-pvs5-bin-v0 =
142 < 1725000000 1100000 >,
143 < 1400000000 1025000 >,
144 < 1000000000 950000 >,
145 < 800000000 900000 >,
146 < 600000000 850000 >,
147 < 384000000 825000 >;
148 qcom,speed0-pvs6-bin-v0 =
149 < 1725000000 1050000 >,
150 < 1400000000 975000 >,
151 < 1000000000 900000 >,
152 < 800000000 850000 >,
153 < 600000000 800000 >,
154 < 384000000 775000 >;
158 #address-cells = <1>;
161 compatible = "simple-bus";
164 compatible = "qcom,lpass-cpu";
166 clocks = <&lcc AHBIX_CLK>,
169 clock-names = "ahbix-clk",
172 interrupts = <0 85 1>;
173 interrupt-names = "lpass-irq-lpaif";
174 reg = <0x28100000 0x10000>;
175 reg-names = "lpass-lpaif";
178 imem: memory@700000 {
179 compatible = "qcom,qfprom", "syscon";
180 reg = <0x00700000 0x1000>;
181 #address-cells = <1>;
184 ranges = <0x0 0x00700000 0x1000>;
188 compatible = "qcom,rpm-ipq8064";
189 reg = <0x108000 0x1000>;
190 qcom,ipc = <&l2cc 0x8 2>;
192 interrupts = <0 19 0>,
195 interrupt-names = "ack",
199 #address-cells = <1>;
203 compatible = "qcom,rpm-smb208-regulators";
206 regulator-min-microvolt = <1050000>;
207 regulator-max-microvolt = <1150000>;
208 qcom,switch-mode-frequency = <1200000>;
212 regulator-min-microvolt = <1050000>;
213 regulator-max-microvolt = <1150000>;
214 qcom,switch-mode-frequency = <1200000>;
218 regulator-min-microvolt = < 800000>;
219 regulator-max-microvolt = <1275000>;
220 qcom,switch-mode-frequency = <1200000>;
224 regulator-min-microvolt = < 800000>;
225 regulator-max-microvolt = <1275000>;
226 qcom,switch-mode-frequency = <1200000>;
232 compatible = "qcom,prng";
233 reg = <0x1a500000 0x200>;
234 clocks = <&gcc PRNG_CLK>;
235 clock-names = "core";
238 qcom,msm-imem@2A03F000 {
239 compatible = "qcom,msm-imem";
240 reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
241 ranges = <0x0 0x2A03F000 0x1000>;
242 #address-cells = <1>;
246 compatible = "qcom,msm-imem-download_mode";
251 compatible = "qcom,msm-imem-restart_reason";
256 compatible = "qcom,msm-imem-l2_dump_offset";
261 qcom_pinmux: pinmux@800000 {
262 compatible = "qcom,ipq8064-pinctrl";
263 reg = <0x800000 0x4000>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
269 interrupts = <0 16 0x4>;
271 pcie0_pins: pcie0_pinmux {
274 function = "pcie1_rst";
275 drive-strength = <12>;
280 pcie1_pins: pcie1_pinmux {
283 function = "pcie2_rst";
284 drive-strength = <12>;
289 pcie2_pins: pcie2_pinmux {
292 function = "pcie3_rst";
293 drive-strength = <12>;
299 intc: interrupt-controller@2000000 {
300 compatible = "qcom,msm-qgic2";
301 interrupt-controller;
302 #interrupt-cells = <3>;
303 reg = <0x02000000 0x1000>,
308 compatible = "qcom,kpss-timer", "qcom,msm-timer";
309 interrupts = <1 1 0x301>,
314 reg = <0x0200a000 0x100>;
315 clock-frequency = <25000000>,
317 clocks = <&sleep_clk>;
318 clock-names = "sleep";
319 cpu-offset = <0x80000>;
322 acc0: clock-controller@2088000 {
323 compatible = "qcom,kpss-acc-v1";
324 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
325 clock-output-names = "acpu0_aux";
328 acc1: clock-controller@2098000 {
329 compatible = "qcom,kpss-acc-v1";
330 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
331 clock-output-names = "acpu1_aux";
334 l2cc: clock-controller@2011000 {
335 compatible = "qcom,kpss-gcc", "syscon";
336 reg = <0x2011000 0x1000>;
337 clock-output-names = "acpu_l2_aux";
340 saw0: regulator@2089000 {
341 compatible = "qcom,saw2", "syscon";
342 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
346 saw1: regulator@2099000 {
347 compatible = "qcom,saw2", "syscon";
348 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
352 saw_l2: regulator@02012000 {
353 compatible = "qcom,saw2", "syscon";
354 reg = <0x02012000 0x1000>;
358 sic_non_secure: sic-non-secure@12100000 {
359 compatible = "syscon";
360 reg = <0x12100000 0x10000>;
363 gsbi1: gsbi@12440000 {
364 compatible = "qcom,gsbi-v1.0.0";
366 reg = <0x12440000 0x100>;
367 clocks = <&gcc GSBI1_H_CLK>;
368 clock-names = "iface";
369 #address-cells = <1>;
374 syscon-tcsr = <&tcsr>;
376 uart1: serial@12450000 {
377 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
378 reg = <0x12450000 0x1000>,
380 interrupts = <0 193 0x0>;
381 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
382 clock-names = "core", "iface";
387 compatible = "qcom,i2c-qup-v1.1.1";
388 reg = <0x12460000 0x1000>;
389 interrupts = <0 194 0>;
391 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
392 clock-names = "core", "iface";
395 #address-cells = <1>;
401 gsbi2: gsbi@12480000 {
402 compatible = "qcom,gsbi-v1.0.0";
404 reg = <0x12480000 0x100>;
405 clocks = <&gcc GSBI2_H_CLK>;
406 clock-names = "iface";
407 #address-cells = <1>;
412 syscon-tcsr = <&tcsr>;
414 uart2: serial@12490000 {
415 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
416 reg = <0x12490000 0x1000>,
418 interrupts = <0 195 0x0>;
419 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
420 clock-names = "core", "iface";
425 compatible = "qcom,i2c-qup-v1.1.1";
426 reg = <0x124a0000 0x1000>;
427 interrupts = <0 196 0>;
429 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
430 clock-names = "core", "iface";
433 #address-cells = <1>;
439 gsbi4: gsbi@16300000 {
440 compatible = "qcom,gsbi-v1.0.0";
442 reg = <0x16300000 0x100>;
443 clocks = <&gcc GSBI4_H_CLK>;
444 clock-names = "iface";
445 #address-cells = <1>;
450 syscon-tcsr = <&tcsr>;
452 uart4: serial@16340000 {
453 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
454 reg = <0x16340000 0x1000>,
456 interrupts = <0 152 0x0>;
457 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
458 clock-names = "core", "iface";
463 compatible = "qcom,i2c-qup-v1.1.1";
464 reg = <0x16380000 0x1000>;
465 interrupts = <0 153 0>;
467 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
468 clock-names = "core", "iface";
471 #address-cells = <1>;
476 gsbi5: gsbi@1a200000 {
477 compatible = "qcom,gsbi-v1.0.0";
479 reg = <0x1a200000 0x100>;
480 clocks = <&gcc GSBI5_H_CLK>;
481 clock-names = "iface";
482 #address-cells = <1>;
487 syscon-tcsr = <&tcsr>;
489 uart5: serial@1a240000 {
490 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
491 reg = <0x1a240000 0x1000>,
493 interrupts = <0 154 0x0>;
494 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
495 clock-names = "core", "iface";
500 compatible = "qcom,i2c-qup-v1.1.1";
501 reg = <0x1a280000 0x1000>;
502 interrupts = <0 155 0>;
504 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
505 clock-names = "core", "iface";
508 #address-cells = <1>;
513 compatible = "qcom,spi-qup-v1.1.1";
514 reg = <0x1a280000 0x1000>;
515 interrupts = <0 155 0>;
517 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
518 clock-names = "core", "iface";
521 #address-cells = <1>;
526 gsbi6: gsbi@16500000 {
527 compatible = "qcom,gsbi-v1.0.0";
529 reg = <0x16500000 0x100>;
530 clocks = <&gcc GSBI6_H_CLK>;
531 clock-names = "iface";
532 #address-cells = <1>;
537 syscon-tcsr = <&tcsr>;
539 uart6: serial@16540000 {
540 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
541 reg = <0x16540000 0x1000>,
543 interrupts = <0 156 0x0>;
544 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
545 clock-names = "core", "iface";
550 compatible = "qcom,i2c-qup-v1.1.1";
551 reg = <0x16580000 0x1000>;
552 interrupts = <0 157 0>;
554 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
555 clock-names = "core", "iface";
558 #address-cells = <1>;
563 compatible = "qcom,spi-qup-v1.1.1";
564 reg = <0x16580000 0x1000>;
565 interrupts = <0 157 0>;
567 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
568 clock-names = "core", "iface";
571 #address-cells = <1>;
576 gsbi7: gsbi@16600000 {
577 compatible = "qcom,gsbi-v1.0.0";
579 reg = <0x16600000 0x100>;
580 clocks = <&gcc GSBI7_H_CLK>;
581 clock-names = "iface";
582 #address-cells = <1>;
587 syscon-tcsr = <&tcsr>;
589 uart7: serial@16640000 {
590 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
591 reg = <0x16640000 0x1000>,
593 interrupts = <0 158 0x0>;
594 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
595 clock-names = "core", "iface";
600 compatible = "qcom,i2c-qup-v1.1.1";
601 reg = <0x16680000 0x1000>;
602 interrupts = <0 159 0>;
604 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
605 clock-names = "core", "iface";
608 #address-cells = <1>;
614 sata_phy: sata-phy@1b400000 {
615 compatible = "qcom,ipq806x-sata-phy";
616 reg = <0x1b400000 0x200>;
618 clocks = <&gcc SATA_PHY_CFG_CLK>;
626 compatible = "qcom,ipq806x-ahci", "generic-ahci";
627 reg = <0x29000000 0x180>;
629 interrupts = <0 209 0x0>;
631 clocks = <&gcc SFAB_SATA_S_H_CLK>,
634 <&gcc SATA_RXOOB_CLK>,
635 <&gcc SATA_PMALIVE_CLK>;
636 clock-names = "slave_face", "iface", "core",
639 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
640 assigned-clock-rates = <100000000>, <100000000>;
643 phy-names = "sata-phy";
648 compatible = "qcom,ssbi";
649 reg = <0x00500000 0x1000>;
650 qcom,controller-type = "pmic-arbiter";
653 gcc: clock-controller@900000 {
654 compatible = "qcom,gcc-ipq8064";
655 reg = <0x00900000 0x4000>;
658 #power-domain-cells = <1>;
661 lcc: clock-controller@28000000 {
662 compatible = "qcom,lcc-ipq8064";
663 reg = <0x28000000 0x1000>;
668 tcsr: syscon@1a400000 {
669 compatible = "qcom,tcsr-ipq8064", "syscon";
670 reg = <0x1a400000 0x100>;
673 tsens: tsens-ipq806x {
674 compatible = "qcom,ipq806x-tsens";
675 reg = <0x900000 0x3678>, <0x700000 0x420>;
676 reg-names = "tsens_physical", "tsens_eeprom_physical";
677 interrupts = <0 178 0>;
679 qcom,tsens_factor = <1000>;
680 qcom,slope = <1176 1176 1154 1176 1111 1132 1132 1199 1132 1199 1132>;
684 compatible = "qcom,msm-thermal";
685 qcom,sensor-id = <0>;
686 qcom,poll-ms = <250>;
687 qcom,limit-temp = <105>;
688 qcom,temp-hysteresis = <10>;
689 qcom,freq-step = <2>;
690 qcom,core-limit-temp = <115>;
691 qcom,core-temp-hysteresis = <10>;
692 qcom,core-control-mask = <0xe>;
695 sfpb_mutex_block: syscon@1200600 {
696 compatible = "syscon";
697 reg = <0x01200600 0x100>;
700 hs_phy_1: phy@100f8800 {
701 compatible = "qcom,dwc3-hs-usb-phy";
702 reg = <0x100f8800 0x30>;
703 clocks = <&gcc USB30_1_UTMI_CLK>;
710 ss_phy_1: phy@100f8830 {
711 compatible = "qcom,dwc3-ss-usb-phy";
712 reg = <0x100f8830 0x30>;
713 clocks = <&gcc USB30_1_MASTER_CLK>;
720 hs_phy_0: phy@110f8800 {
721 compatible = "qcom,dwc3-hs-usb-phy";
722 reg = <0x110f8800 0x30>;
723 clocks = <&gcc USB30_0_UTMI_CLK>;
730 ss_phy_0: phy@110f8830 {
731 compatible = "qcom,dwc3-ss-usb-phy";
732 reg = <0x110f8830 0x30>;
733 clocks = <&gcc USB30_0_MASTER_CLK>;
741 compatible = "qcom,dwc3";
742 #address-cells = <1>;
744 clocks = <&gcc USB30_0_MASTER_CLK>;
745 clock-names = "core";
750 resets = <&gcc USB30_0_MASTER_RESET>;
751 reset-names = "usb30_mstr_rst";
754 compatible = "snps,dwc3";
755 reg = <0x11000000 0xcd00>;
756 interrupts = <0 110 0x4>;
757 phys = <&hs_phy_0>, <&ss_phy_0>;
758 phy-names = "usb2-phy", "usb3-phy";
765 compatible = "qcom,dwc3";
766 #address-cells = <1>;
768 clocks = <&gcc USB30_1_MASTER_CLK>;
769 clock-names = "core";
776 compatible = "snps,dwc3";
777 reg = <0x10000000 0xcd00>;
778 interrupts = <0 205 0x4>;
779 phys = <&hs_phy_1>, <&ss_phy_1>;
780 phy-names = "usb2-phy", "usb3-phy";
786 pcie0: pci@1b500000 {
787 compatible = "qcom,pcie-v0";
788 reg = <0x1b500000 0x1000
791 0x0ff00000 0x100000>;
792 reg-names = "dbi", "elbi", "parf", "config";
794 linux,pci-domain = <0>;
795 bus-range = <0x00 0xff>;
797 #address-cells = <3>;
800 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
801 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
803 interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
804 interrupt-names = "msi";
805 #interrupt-cells = <1>;
806 interrupt-map-mask = <0 0 0 0x7>;
807 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
808 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
809 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
810 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
812 clocks = <&gcc PCIE_A_CLK>,
816 <&gcc PCIE_ALT_REF_CLK>;
817 clock-names = "core", "iface", "phy", "aux", "ref";
819 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
820 assigned-clock-rates = <100000000>;
822 resets = <&gcc PCIE_ACLK_RESET>,
823 <&gcc PCIE_HCLK_RESET>,
824 <&gcc PCIE_POR_RESET>,
825 <&gcc PCIE_PCI_RESET>,
826 <&gcc PCIE_PHY_RESET>,
827 <&gcc PCIE_EXT_RESET>;
828 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
830 pinctrl-0 = <&pcie0_pins>;
831 pinctrl-names = "default";
833 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
838 pcie1: pci@1b700000 {
839 compatible = "qcom,pcie-v0";
840 reg = <0x1b700000 0x1000
843 0x31f00000 0x100000>;
844 reg-names = "dbi", "elbi", "parf", "config";
846 linux,pci-domain = <1>;
847 bus-range = <0x00 0xff>;
849 #address-cells = <3>;
852 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
853 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
855 interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
856 interrupt-names = "msi";
857 #interrupt-cells = <1>;
858 interrupt-map-mask = <0 0 0 0x7>;
859 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
860 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
861 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
862 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
864 clocks = <&gcc PCIE_1_A_CLK>,
866 <&gcc PCIE_1_PHY_CLK>,
867 <&gcc PCIE_1_AUX_CLK>,
868 <&gcc PCIE_1_ALT_REF_CLK>;
869 clock-names = "core", "iface", "phy", "aux", "ref";
871 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
872 assigned-clock-rates = <100000000>;
874 resets = <&gcc PCIE_1_ACLK_RESET>,
875 <&gcc PCIE_1_HCLK_RESET>,
876 <&gcc PCIE_1_POR_RESET>,
877 <&gcc PCIE_1_PCI_RESET>,
878 <&gcc PCIE_1_PHY_RESET>,
879 <&gcc PCIE_1_EXT_RESET>;
880 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
882 pinctrl-0 = <&pcie1_pins>;
883 pinctrl-names = "default";
885 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
890 pcie2: pci@1b900000 {
891 compatible = "qcom,pcie-v0";
892 reg = <0x1b900000 0x1000
895 0x35f00000 0x100000>;
896 reg-names = "dbi", "elbi", "parf", "config";
898 linux,pci-domain = <2>;
899 bus-range = <0x00 0xff>;
901 #address-cells = <3>;
904 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
905 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
907 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
908 interrupt-names = "msi";
909 #interrupt-cells = <1>;
910 interrupt-map-mask = <0 0 0 0x7>;
911 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
912 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
913 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
914 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
916 clocks = <&gcc PCIE_2_A_CLK>,
918 <&gcc PCIE_2_PHY_CLK>,
919 <&gcc PCIE_2_AUX_CLK>,
920 <&gcc PCIE_2_ALT_REF_CLK>;
921 clock-names = "core", "iface", "phy", "aux", "ref";
923 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
924 assigned-clock-rates = <100000000>;
926 resets = <&gcc PCIE_2_ACLK_RESET>,
927 <&gcc PCIE_2_HCLK_RESET>,
928 <&gcc PCIE_2_POR_RESET>,
929 <&gcc PCIE_2_PCI_RESET>,
930 <&gcc PCIE_2_PHY_RESET>,
931 <&gcc PCIE_2_EXT_RESET>;
932 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
934 pinctrl-0 = <&pcie2_pins>;
935 pinctrl-names = "default";
937 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
942 adm_dma: dma@18300000 {
943 compatible = "qcom,adm";
944 reg = <0x18300000 0x100000>;
945 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
948 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
949 clock-names = "core", "iface";
951 resets = <&gcc ADM0_RESET>,
952 <&gcc ADM0_PBUS_RESET>,
953 <&gcc ADM0_C0_RESET>,
954 <&gcc ADM0_C1_RESET>,
955 <&gcc ADM0_C2_RESET>;
956 reset-names = "clk", "pbus", "c0", "c1", "c2";
963 compatible = "qcom,ebi2-nandc";
964 reg = <0x1ac00000 0x800>;
966 clocks = <&gcc EBI2_CLK>,
968 clock-names = "core", "aon";
972 qcom,cmd-crci = <15>;
973 qcom,data-crci = <3>;
978 nss_common: syscon@03000000 {
979 compatible = "syscon";
980 reg = <0x03000000 0x0000FFFF>;
983 qsgmii_csr: syscon@1bb00000 {
984 compatible = "syscon";
985 reg = <0x1bb00000 0x000001FF>;
988 gmac0: ethernet@37000000 {
989 device_type = "network";
990 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
991 reg = <0x37000000 0x200000>;
992 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "macirq";
995 qcom,nss-common = <&nss_common>;
996 qcom,qsgmii-csr = <&qsgmii_csr>;
998 clocks = <&gcc GMAC_CORE1_CLK>;
999 clock-names = "stmmaceth";
1001 resets = <&gcc GMAC_CORE1_RESET>;
1002 reset-names = "stmmaceth";
1004 status = "disabled";
1007 gmac1: ethernet@37200000 {
1008 device_type = "network";
1009 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1010 reg = <0x37200000 0x200000>;
1011 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1012 interrupt-names = "macirq";
1014 qcom,nss-common = <&nss_common>;
1015 qcom,qsgmii-csr = <&qsgmii_csr>;
1017 clocks = <&gcc GMAC_CORE2_CLK>;
1018 clock-names = "stmmaceth";
1020 resets = <&gcc GMAC_CORE2_RESET>;
1021 reset-names = "stmmaceth";
1023 status = "disabled";
1026 gmac2: ethernet@37400000 {
1027 device_type = "network";
1028 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1029 reg = <0x37400000 0x200000>;
1030 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1031 interrupt-names = "macirq";
1033 qcom,nss-common = <&nss_common>;
1034 qcom,qsgmii-csr = <&qsgmii_csr>;
1036 clocks = <&gcc GMAC_CORE3_CLK>;
1037 clock-names = "stmmaceth";
1039 resets = <&gcc GMAC_CORE3_RESET>;
1040 reset-names = "stmmaceth";
1042 status = "disabled";
1045 gmac3: ethernet@37600000 {
1046 device_type = "network";
1047 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1048 reg = <0x37600000 0x200000>;
1049 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1050 interrupt-names = "macirq";
1052 qcom,nss-common = <&nss_common>;
1053 qcom,qsgmii-csr = <&qsgmii_csr>;
1055 clocks = <&gcc GMAC_CORE4_CLK>;
1056 clock-names = "stmmaceth";
1058 resets = <&gcc GMAC_CORE4_RESET>;
1059 reset-names = "stmmaceth";
1061 status = "disabled";
1064 /* Temporary fixed regulator */
1065 vsdcc_fixed: vsdcc-regulator {
1066 compatible = "regulator-fixed";
1067 regulator-name = "SDCC Power";
1068 regulator-min-microvolt = <3300000>;
1069 regulator-max-microvolt = <3300000>;
1070 regulator-always-on;
1073 sdcc1bam:dma@12402000 {
1074 compatible = "qcom,bam-v1.3.0";
1075 reg = <0x12402000 0x8000>;
1076 interrupts = <0 98 0>;
1077 clocks = <&gcc SDC1_H_CLK>;
1078 clock-names = "bam_clk";
1083 sdcc3bam:dma@12182000 {
1084 compatible = "qcom,bam-v1.3.0";
1085 reg = <0x12182000 0x8000>;
1086 interrupts = <0 96 0>;
1087 clocks = <&gcc SDC3_H_CLK>;
1088 clock-names = "bam_clk";
1094 compatible = "arm,amba-bus";
1095 #address-cells = <1>;
1098 sdcc1: sdcc@12400000 {
1099 status = "disabled";
1100 compatible = "arm,pl18x", "arm,primecell";
1101 arm,primecell-periphid = <0x00051180>;
1102 reg = <0x12400000 0x2000>;
1103 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1104 interrupt-names = "cmd_irq";
1105 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1106 clock-names = "mclk", "apb_pclk";
1108 max-frequency = <48000000>;
1112 vmmc-supply = <&vsdcc_fixed>;
1113 #dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1114 #dma-names = "tx", "rx";
1117 sdcc3: sdcc@12180000 {
1118 compatible = "arm,pl18x", "arm,primecell";
1119 arm,primecell-periphid = <0x00051180>;
1120 status = "disabled";
1121 reg = <0x12180000 0x2000>;
1122 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1123 interrupt-names = "cmd_irq";
1124 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1125 clock-names = "mclk", "apb_pclk";
1129 max-frequency = <192000000>;
1132 vmmc-supply = <&vsdcc_fixed>;
1133 #dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1134 #dma-names = "tx", "rx";
1139 sfpb_mutex: sfpb-mutex {
1140 compatible = "qcom,sfpb-mutex";
1141 syscon = <&sfpb_mutex_block 4 4>;
1143 #hwlock-cells = <1>;
1147 compatible = "qcom,smem";
1148 memory-region = <&smem>;
1149 hwlocks = <&sfpb_mutex 3>;