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[openwrt/staging/dedeckeh.git] / target / linux / ipq806x / files-4.19 / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acc0>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 voltage-tolerance = <5>;
35 cooling-min-state = <0>;
36 cooling-max-state = <10>;
37 #cooling-cells = <2>;
38 cpu-idle-states = <&CPU_SPC>;
39 };
40
41 cpu1: cpu@1 {
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
44 device_type = "cpu";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 qcom,acc = <&acc1>;
48 qcom,saw = <&saw1>;
49 clocks = <&kraitcc 1>, <&kraitcc 4>;
50 clock-names = "cpu", "l2";
51 clock-latency = <100000>;
52 cpu-supply = <&smb208_s2b>;
53 voltage-tolerance = <5>;
54 cooling-min-state = <0>;
55 cooling-max-state = <10>;
56 #cooling-cells = <2>;
57 cpu-idle-states = <&CPU_SPC>;
58 };
59
60 L2: l2-cache {
61 compatible = "cache";
62 cache-level = <2>;
63 qcom,saw = <&saw_l2>;
64 };
65
66 qcom,l2 {
67 qcom,l2-rates = <384000000 1000000000 1200000000>;
68 };
69
70 idle-states {
71 CPU_SPC: spc {
72 compatible = "qcom,idle-state-spc",
73 "arm,idle-state";
74 status = "okay";
75 entry-latency-us = <400>;
76 exit-latency-us = <900>;
77 min-residency-us = <3000>;
78 };
79 };
80 };
81
82 thermal-zones {
83 tsens_tz_sensor0 {
84 polling-delay-passive = <0>;
85 polling-delay = <0>;
86 thermal-sensors = <&tsens 0>;
87
88 trips {
89 cpu-critical-hi {
90 temperature = <125000>;
91 hysteresis = <2000>;
92 type = "critical_high";
93 };
94
95 cpu-config-hi {
96 temperature = <105000>;
97 hysteresis = <2000>;
98 type = "configurable_hi";
99 };
100
101 cpu-config-lo {
102 temperature = <95000>;
103 hysteresis = <2000>;
104 type = "configurable_lo";
105 };
106
107 cpu-critical-low {
108 temperature = <0>;
109 hysteresis = <2000>;
110 type = "critical_low";
111 };
112 };
113 };
114
115 tsens_tz_sensor1 {
116 polling-delay-passive = <0>;
117 polling-delay = <0>;
118 thermal-sensors = <&tsens 1>;
119
120 trips {
121 cpu-critical-hi {
122 temperature = <125000>;
123 hysteresis = <2000>;
124 type = "critical_high";
125 };
126
127 cpu-config-hi {
128 temperature = <105000>;
129 hysteresis = <2000>;
130 type = "configurable_hi";
131 };
132
133 cpu-config-lo {
134 temperature = <95000>;
135 hysteresis = <2000>;
136 type = "configurable_lo";
137 };
138
139 cpu-critical-low {
140 temperature = <0>;
141 hysteresis = <2000>;
142 type = "critical_low";
143 };
144 };
145 };
146
147 tsens_tz_sensor2 {
148 polling-delay-passive = <0>;
149 polling-delay = <0>;
150 thermal-sensors = <&tsens 2>;
151
152 trips {
153 cpu-critical-hi {
154 temperature = <125000>;
155 hysteresis = <2000>;
156 type = "critical_high";
157 };
158
159 cpu-config-hi {
160 temperature = <105000>;
161 hysteresis = <2000>;
162 type = "configurable_hi";
163 };
164
165 cpu-config-lo {
166 temperature = <95000>;
167 hysteresis = <2000>;
168 type = "configurable_lo";
169 };
170
171 cpu-critical-low {
172 temperature = <0>;
173 hysteresis = <2000>;
174 type = "critical_low";
175 };
176 };
177 };
178
179 tsens_tz_sensor3 {
180 polling-delay-passive = <0>;
181 polling-delay = <0>;
182 thermal-sensors = <&tsens 3>;
183
184 trips {
185 cpu-critical-hi {
186 temperature = <125000>;
187 hysteresis = <2000>;
188 type = "critical_high";
189 };
190
191 cpu-config-hi {
192 temperature = <105000>;
193 hysteresis = <2000>;
194 type = "configurable_hi";
195 };
196
197 cpu-config-lo {
198 temperature = <95000>;
199 hysteresis = <2000>;
200 type = "configurable_lo";
201 };
202
203 cpu-critical-low {
204 temperature = <0>;
205 hysteresis = <2000>;
206 type = "critical_low";
207 };
208 };
209 };
210
211 tsens_tz_sensor4 {
212 polling-delay-passive = <0>;
213 polling-delay = <0>;
214 thermal-sensors = <&tsens 4>;
215
216 trips {
217 cpu-critical-hi {
218 temperature = <125000>;
219 hysteresis = <2000>;
220 type = "critical_high";
221 };
222
223 cpu-config-hi {
224 temperature = <105000>;
225 hysteresis = <2000>;
226 type = "configurable_hi";
227 };
228
229 cpu-config-lo {
230 temperature = <95000>;
231 hysteresis = <2000>;
232 type = "configurable_lo";
233 };
234
235 cpu-critical-low {
236 temperature = <0>;
237 hysteresis = <2000>;
238 type = "critical_low";
239 };
240 };
241 };
242
243 tsens_tz_sensor5 {
244 polling-delay-passive = <0>;
245 polling-delay = <0>;
246 thermal-sensors = <&tsens 5>;
247
248 trips {
249 cpu-critical-hi {
250 temperature = <125000>;
251 hysteresis = <2000>;
252 type = "critical_high";
253 };
254
255 cpu-config-hi {
256 temperature = <105000>;
257 hysteresis = <2000>;
258 type = "configurable_hi";
259 };
260
261 cpu-config-lo {
262 temperature = <95000>;
263 hysteresis = <2000>;
264 type = "configurable_lo";
265 };
266
267 cpu-critical-low {
268 temperature = <0>;
269 hysteresis = <2000>;
270 type = "critical_low";
271 };
272 };
273 };
274
275 tsens_tz_sensor6 {
276 polling-delay-passive = <0>;
277 polling-delay = <0>;
278 thermal-sensors = <&tsens 6>;
279
280 trips {
281 cpu-critical-hi {
282 temperature = <125000>;
283 hysteresis = <2000>;
284 type = "critical_high";
285 };
286
287 cpu-config-hi {
288 temperature = <105000>;
289 hysteresis = <2000>;
290 type = "configurable_hi";
291 };
292
293 cpu-config-lo {
294 temperature = <95000>;
295 hysteresis = <2000>;
296 type = "configurable_lo";
297 };
298
299 cpu-critical-low {
300 temperature = <0>;
301 hysteresis = <2000>;
302 type = "critical_low";
303 };
304 };
305 };
306
307 tsens_tz_sensor7 {
308 polling-delay-passive = <0>;
309 polling-delay = <0>;
310 thermal-sensors = <&tsens 7>;
311
312 trips {
313 cpu-critical-hi {
314 temperature = <125000>;
315 hysteresis = <2000>;
316 type = "critical_high";
317 };
318
319 cpu-config-hi {
320 temperature = <105000>;
321 hysteresis = <2000>;
322 type = "configurable_hi";
323 };
324
325 cpu-config-lo {
326 temperature = <95000>;
327 hysteresis = <2000>;
328 type = "configurable_lo";
329 };
330
331 cpu-critical-low {
332 temperature = <0>;
333 hysteresis = <2000>;
334 type = "critical_low";
335 };
336 };
337 };
338
339 tsens_tz_sensor8 {
340 polling-delay-passive = <0>;
341 polling-delay = <0>;
342 thermal-sensors = <&tsens 8>;
343
344 trips {
345 cpu-critical-hi {
346 temperature = <125000>;
347 hysteresis = <2000>;
348 type = "critical_high";
349 };
350
351 cpu-config-hi {
352 temperature = <105000>;
353 hysteresis = <2000>;
354 type = "configurable_hi";
355 };
356
357 cpu-config-lo {
358 temperature = <95000>;
359 hysteresis = <2000>;
360 type = "configurable_lo";
361 };
362
363 cpu-critical-low {
364 temperature = <0>;
365 hysteresis = <2000>;
366 type = "critical_low";
367 };
368 };
369 };
370
371 tsens_tz_sensor9 {
372 polling-delay-passive = <0>;
373 polling-delay = <0>;
374 thermal-sensors = <&tsens 9>;
375
376 trips {
377 cpu-critical-hi {
378 temperature = <125000>;
379 hysteresis = <2000>;
380 type = "critical_high";
381 };
382
383 cpu-config-hi {
384 temperature = <105000>;
385 hysteresis = <2000>;
386 type = "configurable_hi";
387 };
388
389 cpu-config-lo {
390 temperature = <95000>;
391 hysteresis = <2000>;
392 type = "configurable_lo";
393 };
394
395 cpu-critical-low {
396 temperature = <0>;
397 hysteresis = <2000>;
398 type = "critical_low";
399 };
400 };
401 };
402
403 tsens_tz_sensor10 {
404 polling-delay-passive = <0>;
405 polling-delay = <0>;
406 thermal-sensors = <&tsens 10>;
407
408 trips {
409 cpu-critical-hi {
410 temperature = <125000>;
411 hysteresis = <2000>;
412 type = "critical_high";
413 };
414
415 cpu-config-hi {
416 temperature = <105000>;
417 hysteresis = <2000>;
418 type = "configurable_hi";
419 };
420
421 cpu-config-lo {
422 temperature = <95000>;
423 hysteresis = <2000>;
424 type = "configurable_lo";
425 };
426
427 cpu-critical-low {
428 temperature = <0>;
429 hysteresis = <2000>;
430 type = "critical_low";
431 };
432 };
433 };
434 };
435
436 cpu-pmu {
437 compatible = "qcom,krait-pmu";
438 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
439 IRQ_TYPE_LEVEL_HIGH)>;
440 };
441
442 reserved-memory {
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges;
446
447 nss@40000000 {
448 reg = <0x40000000 0x1000000>;
449 no-map;
450 };
451
452 smem: smem@41000000 {
453 reg = <0x41000000 0x200000>;
454 no-map;
455 };
456 };
457
458 clocks {
459 cxo_board {
460 compatible = "fixed-clock";
461 #clock-cells = <0>;
462 clock-frequency = <25000000>;
463 };
464
465 pxo_board {
466 compatible = "fixed-clock";
467 #clock-cells = <0>;
468 clock-frequency = <25000000>;
469 };
470
471 sleep_clk: sleep_clk {
472 compatible = "fixed-clock";
473 clock-frequency = <32768>;
474 #clock-cells = <0>;
475 };
476 };
477
478 firmware {
479 scm {
480 compatible = "qcom,scm-ipq806x";
481 };
482 };
483
484 kraitcc: clock-controller {
485 compatible = "qcom,krait-cc-v1";
486 #clock-cells = <1>;
487 };
488
489 qcom,pvs {
490 qcom,pvs-format-a;
491 qcom,speed0-pvs0-bin-v0 =
492 < 1400000000 1250000 >,
493 < 1200000000 1200000 >,
494 < 1000000000 1150000 >,
495 < 800000000 1100000 >,
496 < 600000000 1050000 >,
497 < 384000000 1000000 >;
498
499 qcom,speed0-pvs1-bin-v0 =
500 < 1400000000 1175000 >,
501 < 1200000000 1125000 >,
502 < 1000000000 1075000 >,
503 < 800000000 1025000 >,
504 < 600000000 975000 >,
505 < 384000000 925000 >;
506
507 qcom,speed0-pvs2-bin-v0 =
508 < 1400000000 1125000 >,
509 < 1200000000 1075000 >,
510 < 1000000000 1025000 >,
511 < 800000000 995000 >,
512 < 600000000 925000 >,
513 < 384000000 875000 >;
514
515 qcom,speed0-pvs3-bin-v0 =
516 < 1400000000 1050000 >,
517 < 1200000000 1000000 >,
518 < 1000000000 950000 >,
519 < 800000000 900000 >,
520 < 600000000 850000 >,
521 < 384000000 800000 >;
522 };
523
524 soc: soc {
525 #address-cells = <1>;
526 #size-cells = <1>;
527 ranges;
528 compatible = "simple-bus";
529
530 lpass@28100000 {
531 compatible = "qcom,lpass-cpu";
532 status = "disabled";
533 clocks = <&lcc AHBIX_CLK>,
534 <&lcc MI2S_OSR_CLK>,
535 <&lcc MI2S_BIT_CLK>;
536 clock-names = "ahbix-clk",
537 "mi2s-osr-clk",
538 "mi2s-bit-clk";
539 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
540 interrupt-names = "lpass-irq-lpaif";
541 reg = <0x28100000 0x10000>;
542 reg-names = "lpass-lpaif";
543 };
544
545 qfprom: qfprom@700000 {
546 compatible = "qcom,qfprom", "syscon";
547 reg = <0x700000 0x1000>;
548 #address-cells = <1>;
549 #size-cells = <1>;
550 status = "okay";
551 tsens_calib: calib@400 {
552 reg = <0x400 0x10>;
553 };
554 tsens_backup: backup@410 {
555 reg = <0x410 0x10>;
556 };
557 };
558
559 rpm@108000 {
560 compatible = "qcom,rpm-ipq8064";
561 reg = <0x108000 0x1000>;
562 qcom,ipc = <&l2cc 0x8 2>;
563
564 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-names = "ack",
568 "err",
569 "wakeup";
570
571 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
572 clock-names = "ram";
573
574 #address-cells = <1>;
575 #size-cells = <0>;
576
577 rpmcc: clock-controller {
578 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
579 #clock-cells = <1>;
580 };
581
582 regulators {
583 compatible = "qcom,rpm-smb208-regulators";
584
585 smb208_s1a: s1a {
586 regulator-min-microvolt = <1050000>;
587 regulator-max-microvolt = <1150000>;
588
589 qcom,switch-mode-frequency = <1200000>;
590
591 };
592
593 smb208_s1b: s1b {
594 regulator-min-microvolt = <1050000>;
595 regulator-max-microvolt = <1150000>;
596
597 qcom,switch-mode-frequency = <1200000>;
598 };
599
600 smb208_s2a: s2a {
601 regulator-min-microvolt = < 800000>;
602 regulator-max-microvolt = <1250000>;
603
604 qcom,switch-mode-frequency = <1200000>;
605 };
606
607 smb208_s2b: s2b {
608 regulator-min-microvolt = < 800000>;
609 regulator-max-microvolt = <1250000>;
610
611 qcom,switch-mode-frequency = <1200000>;
612 };
613 };
614 };
615
616 rng@1a500000 {
617 compatible = "qcom,prng";
618 reg = <0x1a500000 0x200>;
619 clocks = <&gcc PRNG_CLK>;
620 clock-names = "core";
621 };
622
623 qcom_pinmux: pinmux@800000 {
624 compatible = "qcom,ipq8064-pinctrl";
625 reg = <0x800000 0x4000>;
626
627 gpio-controller;
628 #gpio-cells = <2>;
629 interrupt-controller;
630 #interrupt-cells = <2>;
631 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
632
633 pcie0_pins: pcie0_pinmux {
634 mux {
635 pins = "gpio3";
636 function = "pcie1_rst";
637 drive-strength = <12>;
638 bias-disable;
639 };
640 };
641
642 pcie1_pins: pcie1_pinmux {
643 mux {
644 pins = "gpio48";
645 function = "pcie2_rst";
646 drive-strength = <12>;
647 bias-disable;
648 };
649 };
650
651 pcie2_pins: pcie2_pinmux {
652 mux {
653 pins = "gpio63";
654 function = "pcie3_rst";
655 drive-strength = <12>;
656 bias-disable;
657 output-low;
658 };
659 };
660
661 spi_pins: spi_pins {
662 mux {
663 pins = "gpio18", "gpio19", "gpio21";
664 function = "gsbi5";
665 drive-strength = <10>;
666 bias-none;
667 };
668 };
669
670 leds_pins: leds_pins {
671 mux {
672 pins = "gpio7", "gpio8", "gpio9",
673 "gpio26", "gpio53";
674 function = "gpio";
675 drive-strength = <2>;
676 bias-pull-down;
677 output-low;
678 };
679 };
680
681 buttons_pins: buttons_pins {
682 mux {
683 pins = "gpio54";
684 drive-strength = <2>;
685 bias-pull-up;
686 };
687 };
688 };
689
690 intc: interrupt-controller@2000000 {
691 compatible = "qcom,msm-qgic2";
692 interrupt-controller;
693 #interrupt-cells = <3>;
694 reg = <0x02000000 0x1000>,
695 <0x02002000 0x1000>;
696 };
697
698 timer@200a000 {
699 compatible = "qcom,kpss-timer",
700 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
701 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
702 IRQ_TYPE_EDGE_RISING)>,
703 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
704 IRQ_TYPE_EDGE_RISING)>,
705 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
706 IRQ_TYPE_EDGE_RISING)>,
707 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
708 IRQ_TYPE_EDGE_RISING)>,
709 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
710 IRQ_TYPE_EDGE_RISING)>;
711 reg = <0x0200a000 0x100>;
712 clock-frequency = <25000000>,
713 <32768>;
714 clocks = <&sleep_clk>;
715 clock-names = "sleep";
716 cpu-offset = <0x80000>;
717 };
718
719 acc0: clock-controller@2088000 {
720 compatible = "qcom,kpss-acc-v1";
721 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
722 clock-output-names = "acpu0_aux";
723 };
724
725 acc1: clock-controller@2098000 {
726 compatible = "qcom,kpss-acc-v1";
727 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
728 clock-output-names = "acpu1_aux";
729 };
730
731 l2cc: clock-controller@2011000 {
732 compatible = "qcom,kpss-gcc", "syscon";
733 reg = <0x2011000 0x1000>;
734 clock-output-names = "acpu_l2_aux";
735 };
736
737 saw0: regulator@2089000 {
738 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
739 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
740 regulator;
741 };
742
743 saw1: regulator@2099000 {
744 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
745 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
746 regulator;
747 };
748
749 saw_l2: regulator@02012000 {
750 compatible = "qcom,saw2", "syscon";
751 reg = <0x02012000 0x1000>;
752 regulator;
753 };
754
755 sic_non_secure: sic-non-secure@12100000 {
756 compatible = "syscon";
757 reg = <0x12100000 0x10000>;
758 };
759
760 gsbi2: gsbi@12480000 {
761 compatible = "qcom,gsbi-v1.0.0";
762 cell-index = <2>;
763 reg = <0x12480000 0x100>;
764 clocks = <&gcc GSBI2_H_CLK>;
765 clock-names = "iface";
766 #address-cells = <1>;
767 #size-cells = <1>;
768 ranges;
769 status = "disabled";
770
771 syscon-tcsr = <&tcsr>;
772
773 uart2: serial@12490000 {
774 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
775 reg = <0x12490000 0x1000>,
776 <0x12480000 0x1000>;
777 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
779 clock-names = "core", "iface";
780 status = "disabled";
781 };
782
783 i2c@124a0000 {
784 compatible = "qcom,i2c-qup-v1.1.1";
785 reg = <0x124a0000 0x1000>;
786 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
787
788 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
789 clock-names = "core", "iface";
790 status = "disabled";
791
792 #address-cells = <1>;
793 #size-cells = <0>;
794 };
795
796 };
797
798 gsbi4: gsbi@16300000 {
799 compatible = "qcom,gsbi-v1.0.0";
800 cell-index = <4>;
801 reg = <0x16300000 0x100>;
802 clocks = <&gcc GSBI4_H_CLK>;
803 clock-names = "iface";
804 #address-cells = <1>;
805 #size-cells = <1>;
806 ranges;
807 status = "disabled";
808
809 syscon-tcsr = <&tcsr>;
810
811 gsbi4_serial: serial@16340000 {
812 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
813 reg = <0x16340000 0x1000>,
814 <0x16300000 0x1000>;
815 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
817 clock-names = "core", "iface";
818 status = "disabled";
819 };
820
821 i2c@16380000 {
822 compatible = "qcom,i2c-qup-v1.1.1";
823 reg = <0x16380000 0x1000>;
824 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
825
826 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
827 clock-names = "core", "iface";
828 status = "disabled";
829
830 #address-cells = <1>;
831 #size-cells = <0>;
832 };
833 };
834
835 gsbi5: gsbi@1a200000 {
836 compatible = "qcom,gsbi-v1.0.0";
837 cell-index = <5>;
838 reg = <0x1a200000 0x100>;
839 clocks = <&gcc GSBI5_H_CLK>;
840 clock-names = "iface";
841 #address-cells = <1>;
842 #size-cells = <1>;
843 ranges;
844 status = "disabled";
845
846 syscon-tcsr = <&tcsr>;
847
848 uart5: serial@1a240000 {
849 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
850 reg = <0x1a240000 0x1000>,
851 <0x1a200000 0x1000>;
852 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
854 clock-names = "core", "iface";
855 status = "disabled";
856 };
857
858 i2c@1a280000 {
859 compatible = "qcom,i2c-qup-v1.1.1";
860 reg = <0x1a280000 0x1000>;
861 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
862
863 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
864 clock-names = "core", "iface";
865 status = "disabled";
866
867 #address-cells = <1>;
868 #size-cells = <0>;
869 };
870
871 spi@1a280000 {
872 compatible = "qcom,spi-qup-v1.1.1";
873 reg = <0x1a280000 0x1000>;
874 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
875
876 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
877 clock-names = "core", "iface";
878 status = "disabled";
879
880 #address-cells = <1>;
881 #size-cells = <0>;
882 };
883 };
884
885 gsbi7: gsbi@16600000 {
886 status = "disabled";
887 compatible = "qcom,gsbi-v1.0.0";
888 cell-index = <7>;
889 reg = <0x16600000 0x100>;
890 clocks = <&gcc GSBI7_H_CLK>;
891 clock-names = "iface";
892 #address-cells = <1>;
893 #size-cells = <1>;
894 ranges;
895 syscon-tcsr = <&tcsr>;
896
897 gsbi7_serial: serial@16640000 {
898 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
899 reg = <0x16640000 0x1000>,
900 <0x16600000 0x1000>;
901 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
902 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
903 clock-names = "core", "iface";
904 status = "disabled";
905 };
906 };
907
908 sata_phy: sata-phy@1b400000 {
909 compatible = "qcom,ipq806x-sata-phy";
910 reg = <0x1b400000 0x200>;
911
912 clocks = <&gcc SATA_PHY_CFG_CLK>;
913 clock-names = "cfg";
914
915 #phy-cells = <0>;
916 status = "disabled";
917 };
918
919 sata: sata@29000000 {
920 compatible = "qcom,ipq806x-ahci", "generic-ahci";
921 reg = <0x29000000 0x180>;
922
923 ports-implemented = <0x1>;
924
925 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
926
927 clocks = <&gcc SFAB_SATA_S_H_CLK>,
928 <&gcc SATA_H_CLK>,
929 <&gcc SATA_A_CLK>,
930 <&gcc SATA_RXOOB_CLK>,
931 <&gcc SATA_PMALIVE_CLK>;
932 clock-names = "slave_face", "iface", "core",
933 "rxoob", "pmalive";
934
935 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
936 assigned-clock-rates = <100000000>, <100000000>;
937
938 phys = <&sata_phy>;
939 phy-names = "sata-phy";
940 status = "disabled";
941 };
942
943 qcom,ssbi@500000 {
944 compatible = "qcom,ssbi";
945 reg = <0x00500000 0x1000>;
946 qcom,controller-type = "pmic-arbiter";
947 };
948
949 gcc: clock-controller@900000 {
950 compatible = "qcom,gcc-ipq8064";
951 reg = <0x00900000 0x4000>;
952 #clock-cells = <1>;
953 #reset-cells = <1>;
954 #power-domain-cells = <1>;
955 };
956
957 tsens: thermal-sensor@900000 {
958 compatible = "qcom,ipq8064-tsens";
959 reg = <0x900000 0x3680>;
960 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
961 nvmem-cell-names = "calib", "calib_backup";
962 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
963 #thermal-sensor-cells = <1>;
964 };
965
966 tcsr: syscon@1a400000 {
967 compatible = "qcom,tcsr-ipq8064", "syscon";
968 reg = <0x1a400000 0x100>;
969 };
970
971 lcc: clock-controller@28000000 {
972 compatible = "qcom,lcc-ipq8064";
973 reg = <0x28000000 0x1000>;
974 #clock-cells = <1>;
975 #reset-cells = <1>;
976 };
977
978 sfpb_mutex_block: syscon@1200600 {
979 compatible = "syscon";
980 reg = <0x01200600 0x100>;
981 };
982
983 hs_phy_0: hs_phy_0 {
984 compatible = "qcom,dwc3-hs-usb-phy";
985 regmap = <&usb3_0>;
986 clocks = <&gcc USB30_0_UTMI_CLK>;
987 clock-names = "ref";
988 #phy-cells = <0>;
989 };
990
991 ss_phy_0: ss_phy_0 {
992 compatible = "qcom,dwc3-ss-usb-phy";
993 regmap = <&usb3_0>;
994 clocks = <&gcc USB30_0_MASTER_CLK>;
995 clock-names = "ref";
996 #phy-cells = <0>;
997 };
998
999 usb3_0: usb3@110f8800 {
1000 compatible = "qcom,dwc3", "syscon";
1001 #address-cells = <1>;
1002 #size-cells = <1>;
1003 reg = <0x110f8800 0x8000>;
1004 clocks = <&gcc USB30_0_MASTER_CLK>;
1005 clock-names = "core";
1006
1007 ranges;
1008
1009 resets = <&gcc USB30_0_MASTER_RESET>;
1010 reset-names = "master";
1011
1012 status = "disabled";
1013
1014 dwc3_0: dwc3@11000000 {
1015 compatible = "snps,dwc3";
1016 reg = <0x11000000 0xcd00>;
1017 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1018 phys = <&hs_phy_0>, <&ss_phy_0>;
1019 phy-names = "usb2-phy", "usb3-phy";
1020 dr_mode = "host";
1021 snps,dis_u3_susphy_quirk;
1022 };
1023 };
1024
1025 hs_phy_1: hs_phy_1 {
1026 compatible = "qcom,dwc3-hs-usb-phy";
1027 regmap = <&usb3_1>;
1028 clocks = <&gcc USB30_1_UTMI_CLK>;
1029 clock-names = "ref";
1030 #phy-cells = <0>;
1031 };
1032
1033 ss_phy_1: ss_phy_1 {
1034 compatible = "qcom,dwc3-ss-usb-phy";
1035 regmap = <&usb3_1>;
1036 clocks = <&gcc USB30_1_MASTER_CLK>;
1037 clock-names = "ref";
1038 #phy-cells = <0>;
1039 };
1040
1041 usb3_1: usb3@100f8800 {
1042 compatible = "qcom,dwc3", "syscon";
1043 #address-cells = <1>;
1044 #size-cells = <1>;
1045 reg = <0x100f8800 0x8000>;
1046 clocks = <&gcc USB30_1_MASTER_CLK>;
1047 clock-names = "core";
1048
1049 ranges;
1050
1051 resets = <&gcc USB30_1_MASTER_RESET>;
1052 reset-names = "master";
1053
1054 status = "disabled";
1055
1056 dwc3_1: dwc3@10000000 {
1057 compatible = "snps,dwc3";
1058 reg = <0x10000000 0xcd00>;
1059 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1060 phys = <&hs_phy_1>, <&ss_phy_1>;
1061 phy-names = "usb2-phy", "usb3-phy";
1062 dr_mode = "host";
1063 snps,dis_u3_susphy_quirk;
1064 };
1065 };
1066
1067 pcie0: pci@1b500000 {
1068 compatible = "qcom,pcie-ipq8064";
1069 reg = <0x1b500000 0x1000
1070 0x1b502000 0x80
1071 0x1b600000 0x100
1072 0x0ff00000 0x100000>;
1073 reg-names = "dbi", "elbi", "parf", "config";
1074 device_type = "pci";
1075 linux,pci-domain = <0>;
1076 bus-range = <0x00 0xff>;
1077 num-lanes = <1>;
1078 #address-cells = <3>;
1079 #size-cells = <2>;
1080
1081 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1082 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1083
1084 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1085 interrupt-names = "msi";
1086 #interrupt-cells = <1>;
1087 interrupt-map-mask = <0 0 0 0x7>;
1088 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1089 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1090 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1091 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1092
1093 clocks = <&gcc PCIE_A_CLK>,
1094 <&gcc PCIE_H_CLK>,
1095 <&gcc PCIE_PHY_CLK>,
1096 <&gcc PCIE_AUX_CLK>,
1097 <&gcc PCIE_ALT_REF_CLK>;
1098 clock-names = "core", "iface", "phy", "aux", "ref";
1099
1100 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1101 assigned-clock-rates = <100000000>;
1102
1103 resets = <&gcc PCIE_ACLK_RESET>,
1104 <&gcc PCIE_HCLK_RESET>,
1105 <&gcc PCIE_POR_RESET>,
1106 <&gcc PCIE_PCI_RESET>,
1107 <&gcc PCIE_PHY_RESET>,
1108 <&gcc PCIE_EXT_RESET>;
1109 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1110
1111 pinctrl-0 = <&pcie0_pins>;
1112 pinctrl-names = "default";
1113
1114 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1115
1116 phy-tx0-term-offset = <7>;
1117
1118 status = "disabled";
1119 };
1120
1121 pcie1: pci@1b700000 {
1122 compatible = "qcom,pcie-ipq8064";
1123 reg = <0x1b700000 0x1000
1124 0x1b702000 0x80
1125 0x1b800000 0x100
1126 0x31f00000 0x100000>;
1127 reg-names = "dbi", "elbi", "parf", "config";
1128 device_type = "pci";
1129 linux,pci-domain = <1>;
1130 bus-range = <0x00 0xff>;
1131 num-lanes = <1>;
1132 #address-cells = <3>;
1133 #size-cells = <2>;
1134
1135 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1136 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1137
1138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1139 interrupt-names = "msi";
1140 #interrupt-cells = <1>;
1141 interrupt-map-mask = <0 0 0 0x7>;
1142 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1143 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1144 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1145 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1146
1147 clocks = <&gcc PCIE_1_A_CLK>,
1148 <&gcc PCIE_1_H_CLK>,
1149 <&gcc PCIE_1_PHY_CLK>,
1150 <&gcc PCIE_1_AUX_CLK>,
1151 <&gcc PCIE_1_ALT_REF_CLK>;
1152 clock-names = "core", "iface", "phy", "aux", "ref";
1153
1154 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1155 assigned-clock-rates = <100000000>;
1156
1157 resets = <&gcc PCIE_1_ACLK_RESET>,
1158 <&gcc PCIE_1_HCLK_RESET>,
1159 <&gcc PCIE_1_POR_RESET>,
1160 <&gcc PCIE_1_PCI_RESET>,
1161 <&gcc PCIE_1_PHY_RESET>,
1162 <&gcc PCIE_1_EXT_RESET>;
1163 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1164
1165 pinctrl-0 = <&pcie1_pins>;
1166 pinctrl-names = "default";
1167
1168 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1169
1170 phy-tx0-term-offset = <7>;
1171
1172 status = "disabled";
1173 };
1174
1175 pcie2: pci@1b900000 {
1176 compatible = "qcom,pcie-ipq8064";
1177 reg = <0x1b900000 0x1000
1178 0x1b902000 0x80
1179 0x1ba00000 0x100
1180 0x35f00000 0x100000>;
1181 reg-names = "dbi", "elbi", "parf", "config";
1182 device_type = "pci";
1183 linux,pci-domain = <2>;
1184 bus-range = <0x00 0xff>;
1185 num-lanes = <1>;
1186 #address-cells = <3>;
1187 #size-cells = <2>;
1188
1189 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1190 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1191
1192 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1193 interrupt-names = "msi";
1194 #interrupt-cells = <1>;
1195 interrupt-map-mask = <0 0 0 0x7>;
1196 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1197 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1198 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1199 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1200
1201 clocks = <&gcc PCIE_2_A_CLK>,
1202 <&gcc PCIE_2_H_CLK>,
1203 <&gcc PCIE_2_PHY_CLK>,
1204 <&gcc PCIE_2_AUX_CLK>,
1205 <&gcc PCIE_2_ALT_REF_CLK>;
1206 clock-names = "core", "iface", "phy", "aux", "ref";
1207
1208 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1209 assigned-clock-rates = <100000000>;
1210
1211 resets = <&gcc PCIE_2_ACLK_RESET>,
1212 <&gcc PCIE_2_HCLK_RESET>,
1213 <&gcc PCIE_2_POR_RESET>,
1214 <&gcc PCIE_2_PCI_RESET>,
1215 <&gcc PCIE_2_PHY_RESET>,
1216 <&gcc PCIE_2_EXT_RESET>;
1217 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1218
1219 pinctrl-0 = <&pcie2_pins>;
1220 pinctrl-names = "default";
1221
1222 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1223
1224 phy-tx0-term-offset = <7>;
1225
1226 status = "disabled";
1227 };
1228
1229 adm_dma: dma@18300000 {
1230 compatible = "qcom,adm";
1231 reg = <0x18300000 0x100000>;
1232 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1233 #dma-cells = <1>;
1234
1235 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1236 clock-names = "core", "iface";
1237
1238 resets = <&gcc ADM0_RESET>,
1239 <&gcc ADM0_PBUS_RESET>,
1240 <&gcc ADM0_C0_RESET>,
1241 <&gcc ADM0_C1_RESET>,
1242 <&gcc ADM0_C2_RESET>;
1243 reset-names = "clk", "pbus", "c0", "c1", "c2";
1244 qcom,ee = <0>;
1245
1246 status = "disabled";
1247 };
1248
1249 nand: nand@1ac00000 {
1250 compatible = "qcom,ipq806x-nand";
1251 reg = <0x1ac00000 0x800>;
1252
1253 clocks = <&gcc EBI2_CLK>,
1254 <&gcc EBI2_AON_CLK>;
1255 clock-names = "core", "aon";
1256
1257 dmas = <&adm_dma 3>;
1258 dma-names = "rxtx";
1259 qcom,cmd-crci = <15>;
1260 qcom,data-crci = <3>;
1261
1262 status = "disabled";
1263
1264 #address-cells = <1>;
1265 #size-cells = <0>;
1266 };
1267
1268 nss_common: syscon@03000000 {
1269 compatible = "syscon";
1270 reg = <0x03000000 0x0000FFFF>;
1271 };
1272
1273 qsgmii_csr: syscon@1bb00000 {
1274 compatible = "syscon";
1275 reg = <0x1bb00000 0x000001FF>;
1276 };
1277
1278 stmmac_axi_setup: stmmac-axi-config {
1279 snps,wr_osr_lmt = <7>;
1280 snps,rd_osr_lmt = <7>;
1281 snps,blen = <16 0 0 0 0 0 0>;
1282 };
1283
1284 gmac0: ethernet@37000000 {
1285 device_type = "network";
1286 compatible = "qcom,ipq806x-gmac";
1287 reg = <0x37000000 0x200000>;
1288 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1289 interrupt-names = "macirq";
1290
1291 snps,axi-config = <&stmmac_axi_setup>;
1292 snps,pbl = <32>;
1293 snps,aal = <1>;
1294
1295 qcom,nss-common = <&nss_common>;
1296 qcom,qsgmii-csr = <&qsgmii_csr>;
1297
1298 clocks = <&gcc GMAC_CORE1_CLK>;
1299 clock-names = "stmmaceth";
1300
1301 resets = <&gcc GMAC_CORE1_RESET>;
1302 reset-names = "stmmaceth";
1303
1304 status = "disabled";
1305 };
1306
1307 gmac1: ethernet@37200000 {
1308 device_type = "network";
1309 compatible = "qcom,ipq806x-gmac";
1310 reg = <0x37200000 0x200000>;
1311 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1312 interrupt-names = "macirq";
1313
1314 snps,axi-config = <&stmmac_axi_setup>;
1315 snps,pbl = <32>;
1316 snps,aal = <1>;
1317
1318 qcom,nss-common = <&nss_common>;
1319 qcom,qsgmii-csr = <&qsgmii_csr>;
1320
1321 clocks = <&gcc GMAC_CORE2_CLK>;
1322 clock-names = "stmmaceth";
1323
1324 resets = <&gcc GMAC_CORE2_RESET>;
1325 reset-names = "stmmaceth";
1326
1327 status = "disabled";
1328 };
1329
1330 gmac2: ethernet@37400000 {
1331 device_type = "network";
1332 compatible = "qcom,ipq806x-gmac";
1333 reg = <0x37400000 0x200000>;
1334 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1335 interrupt-names = "macirq";
1336
1337 snps,axi-config = <&stmmac_axi_setup>;
1338 snps,pbl = <32>;
1339 snps,aal = <1>;
1340
1341 qcom,nss-common = <&nss_common>;
1342 qcom,qsgmii-csr = <&qsgmii_csr>;
1343
1344 clocks = <&gcc GMAC_CORE3_CLK>;
1345 clock-names = "stmmaceth";
1346
1347 resets = <&gcc GMAC_CORE3_RESET>;
1348 reset-names = "stmmaceth";
1349
1350 status = "disabled";
1351 };
1352
1353 gmac3: ethernet@37600000 {
1354 device_type = "network";
1355 compatible = "qcom,ipq806x-gmac";
1356 reg = <0x37600000 0x200000>;
1357 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1358 interrupt-names = "macirq";
1359
1360 snps,axi-config = <&stmmac_axi_setup>;
1361 snps,pbl = <32>;
1362 snps,aal = <1>;
1363
1364 qcom,nss-common = <&nss_common>;
1365 qcom,qsgmii-csr = <&qsgmii_csr>;
1366
1367 clocks = <&gcc GMAC_CORE4_CLK>;
1368 clock-names = "stmmaceth";
1369
1370 resets = <&gcc GMAC_CORE4_RESET>;
1371 reset-names = "stmmaceth";
1372
1373 status = "disabled";
1374 };
1375
1376 /* Temporary fixed regulator */
1377 vsdcc_fixed: vsdcc-regulator {
1378 compatible = "regulator-fixed";
1379 regulator-name = "SDCC Power";
1380 regulator-min-microvolt = <3300000>;
1381 regulator-max-microvolt = <3300000>;
1382 regulator-always-on;
1383 };
1384
1385 sdcc1bam:dma@12402000 {
1386 compatible = "qcom,bam-v1.3.0";
1387 reg = <0x12402000 0x8000>;
1388 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1389 clocks = <&gcc SDC1_H_CLK>;
1390 clock-names = "bam_clk";
1391 #dma-cells = <1>;
1392 qcom,ee = <0>;
1393 };
1394
1395 sdcc3bam:dma@12182000 {
1396 compatible = "qcom,bam-v1.3.0";
1397 reg = <0x12182000 0x8000>;
1398 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1399 clocks = <&gcc SDC3_H_CLK>;
1400 clock-names = "bam_clk";
1401 #dma-cells = <1>;
1402 qcom,ee = <0>;
1403 };
1404
1405 amba {
1406 compatible = "arm,amba-bus";
1407 #address-cells = <1>;
1408 #size-cells = <1>;
1409 ranges;
1410 sdcc1: sdcc@12400000 {
1411 status = "disabled";
1412 compatible = "arm,pl18x", "arm,primecell";
1413 arm,primecell-periphid = <0x00051180>;
1414 reg = <0x12400000 0x2000>;
1415 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1416 interrupt-names = "cmd_irq";
1417 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1418 clock-names = "mclk", "apb_pclk";
1419 bus-width = <8>;
1420 max-frequency = <96000000>;
1421 non-removable;
1422 cap-sd-highspeed;
1423 cap-mmc-highspeed;
1424 vmmc-supply = <&vsdcc_fixed>;
1425 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1426 dma-names = "tx", "rx";
1427 };
1428
1429 sdcc3: sdcc@12180000 {
1430 compatible = "arm,pl18x", "arm,primecell";
1431 arm,primecell-periphid = <0x00051180>;
1432 status = "disabled";
1433 reg = <0x12180000 0x2000>;
1434 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1435 interrupt-names = "cmd_irq";
1436 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1437 clock-names = "mclk", "apb_pclk";
1438 bus-width = <8>;
1439 cap-sd-highspeed;
1440 cap-mmc-highspeed;
1441 max-frequency = <192000000>;
1442 #mmc-ddr-1_8v;
1443 sd-uhs-sdr104;
1444 sd-uhs-ddr50;
1445 vqmmc-supply = <&vsdcc_fixed>;
1446 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1447 dma-names = "tx", "rx";
1448 };
1449 };
1450 };
1451
1452 sfpb_mutex: sfpb-mutex {
1453 compatible = "qcom,sfpb-mutex";
1454 syscon = <&sfpb_mutex_block 4 4>;
1455
1456 #hwlock-cells = <1>;
1457 };
1458
1459 smem {
1460 compatible = "qcom,smem";
1461 memory-region = <&smem>;
1462 hwlocks = <&sfpb_mutex 3>;
1463 };
1464 };
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