3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
27 next-level-cache = <&L2>;
28 qcom,acc = <&acpu0_aux>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 operating-points-v2 = <&opp_table0>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
39 cpu-idle-states = <&CPU_SPC>;
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
47 next-level-cache = <&L2>;
48 qcom,acc = <&acpu1_aux>;
50 clocks = <&kraitcc 1>, <&kraitcc 4>;
51 clock-names = "cpu", "l2";
52 clock-latency = <100000>;
53 cpu-supply = <&smb208_s2b>;
54 operating-points-v2 = <&opp_table0>;
55 voltage-tolerance = <5>;
56 cooling-min-state = <0>;
57 cooling-max-state = <10>;
59 cpu-idle-states = <&CPU_SPC>;
69 qcom,l2-rates = <384000000 1000000000 1200000000>;
74 compatible = "qcom,idle-state-spc",
77 entry-latency-us = <400>;
78 exit-latency-us = <900>;
79 min-residency-us = <3000>;
84 opp_table0: opp_table0 {
85 compatible = "operating-points-v2-qcom-cpu";
86 nvmem-cells = <&speedbin_efuse>;
89 opp-hz = /bits/ 64 <384000000>;
90 opp-microvolt-speed0-pvs0-v0 = <1000000>;
91 opp-microvolt-speed0-pvs1-v0 = <925000>;
92 opp-microvolt-speed0-pvs2-v0 = <875000>;
93 opp-microvolt-speed0-pvs3-v0 = <800000>;
94 opp-supported-hw = <0x1>;
95 clock-latency-ns = <100000>;
99 opp-hz = /bits/ 64 <600000000>;
100 opp-microvolt-speed0-pvs0-v0 = <1050000>;
101 opp-microvolt-speed0-pvs1-v0 = <975000>;
102 opp-microvolt-speed0-pvs2-v0 = <925000>;
103 opp-microvolt-speed0-pvs3-v0 = <850000>;
104 opp-supported-hw = <0x1>;
105 clock-latency-ns = <100000>;
109 opp-hz = /bits/ 64 <800000000>;
110 opp-microvolt-speed0-pvs0-v0 = <1100000>;
111 opp-microvolt-speed0-pvs1-v0 = <1025000>;
112 opp-microvolt-speed0-pvs2-v0 = <995000>;
113 opp-microvolt-speed0-pvs3-v0 = <900000>;
114 opp-supported-hw = <0x1>;
115 clock-latency-ns = <100000>;
119 opp-hz = /bits/ 64 <1000000000>;
120 opp-microvolt-speed0-pvs0-v0 = <1150000>;
121 opp-microvolt-speed0-pvs1-v0 = <1075000>;
122 opp-microvolt-speed0-pvs2-v0 = <1025000>;
123 opp-microvolt-speed0-pvs3-v0 = <950000>;
124 opp-supported-hw = <0x1>;
125 clock-latency-ns = <100000>;
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt-speed0-pvs0-v0 = <1200000>;
131 opp-microvolt-speed0-pvs1-v0 = <1125000>;
132 opp-microvolt-speed0-pvs2-v0 = <1075000>;
133 opp-microvolt-speed0-pvs3-v0 = <1000000>;
134 opp-supported-hw = <0x1>;
135 clock-latency-ns = <100000>;
139 opp-hz = /bits/ 64 <1400000000>;
140 opp-microvolt-speed0-pvs0-v0 = <1250000>;
141 opp-microvolt-speed0-pvs1-v0 = <1175000>;
142 opp-microvolt-speed0-pvs2-v0 = <1125000>;
143 opp-microvolt-speed0-pvs3-v0 = <1050000>;
144 opp-supported-hw = <0x1>;
145 clock-latency-ns = <100000>;
152 polling-delay-passive = <0>;
154 thermal-sensors = <&tsens 0>;
158 temperature = <125000>;
160 type = "critical_high";
164 temperature = <105000>;
166 type = "configurable_hi";
170 temperature = <95000>;
172 type = "configurable_lo";
178 type = "critical_low";
184 polling-delay-passive = <0>;
186 thermal-sensors = <&tsens 1>;
190 temperature = <125000>;
192 type = "critical_high";
196 temperature = <105000>;
198 type = "configurable_hi";
202 temperature = <95000>;
204 type = "configurable_lo";
210 type = "critical_low";
216 polling-delay-passive = <0>;
218 thermal-sensors = <&tsens 2>;
222 temperature = <125000>;
224 type = "critical_high";
228 temperature = <105000>;
230 type = "configurable_hi";
234 temperature = <95000>;
236 type = "configurable_lo";
242 type = "critical_low";
248 polling-delay-passive = <0>;
250 thermal-sensors = <&tsens 3>;
254 temperature = <125000>;
256 type = "critical_high";
260 temperature = <105000>;
262 type = "configurable_hi";
266 temperature = <95000>;
268 type = "configurable_lo";
274 type = "critical_low";
280 polling-delay-passive = <0>;
282 thermal-sensors = <&tsens 4>;
286 temperature = <125000>;
288 type = "critical_high";
292 temperature = <105000>;
294 type = "configurable_hi";
298 temperature = <95000>;
300 type = "configurable_lo";
306 type = "critical_low";
312 polling-delay-passive = <0>;
314 thermal-sensors = <&tsens 5>;
318 temperature = <125000>;
320 type = "critical_high";
324 temperature = <105000>;
326 type = "configurable_hi";
330 temperature = <95000>;
332 type = "configurable_lo";
338 type = "critical_low";
344 polling-delay-passive = <0>;
346 thermal-sensors = <&tsens 6>;
350 temperature = <125000>;
352 type = "critical_high";
356 temperature = <105000>;
358 type = "configurable_hi";
362 temperature = <95000>;
364 type = "configurable_lo";
370 type = "critical_low";
376 polling-delay-passive = <0>;
378 thermal-sensors = <&tsens 7>;
382 temperature = <125000>;
384 type = "critical_high";
388 temperature = <105000>;
390 type = "configurable_hi";
394 temperature = <95000>;
396 type = "configurable_lo";
402 type = "critical_low";
408 polling-delay-passive = <0>;
410 thermal-sensors = <&tsens 8>;
414 temperature = <125000>;
416 type = "critical_high";
420 temperature = <105000>;
422 type = "configurable_hi";
426 temperature = <95000>;
428 type = "configurable_lo";
434 type = "critical_low";
440 polling-delay-passive = <0>;
442 thermal-sensors = <&tsens 9>;
446 temperature = <125000>;
448 type = "critical_high";
452 temperature = <105000>;
454 type = "configurable_hi";
458 temperature = <95000>;
460 type = "configurable_lo";
466 type = "critical_low";
472 polling-delay-passive = <0>;
474 thermal-sensors = <&tsens 10>;
478 temperature = <125000>;
480 type = "critical_high";
484 temperature = <105000>;
486 type = "configurable_hi";
490 temperature = <95000>;
492 type = "configurable_lo";
498 type = "critical_low";
505 compatible = "qcom,krait-pmu";
506 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
507 IRQ_TYPE_LEVEL_HIGH)>;
511 #address-cells = <1>;
516 reg = <0x40000000 0x1000000>;
520 smem: smem@41000000 {
521 reg = <0x41000000 0x200000>;
528 compatible = "fixed-clock";
530 clock-frequency = <25000000>;
534 compatible = "fixed-clock";
536 clock-frequency = <25000000>;
539 sleep_clk: sleep_clk {
540 compatible = "fixed-clock";
541 clock-frequency = <32768>;
548 compatible = "qcom,scm-ipq806x";
553 #address-cells = <1>;
556 compatible = "simple-bus";
559 compatible = "qcom,lpass-cpu";
561 clocks = <&lcc AHBIX_CLK>,
564 clock-names = "ahbix-clk",
567 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
568 interrupt-names = "lpass-irq-lpaif";
569 reg = <0x28100000 0x10000>;
570 reg-names = "lpass-lpaif";
573 qfprom: qfprom@700000 {
574 compatible = "qcom,qfprom", "syscon";
575 reg = <0x700000 0x1000>;
576 #address-cells = <1>;
579 tsens_calib: calib@400 {
582 tsens_backup: backup@410 {
585 speedbin_efuse: speedbin@0c0 {
591 compatible = "qcom,rpm-ipq8064";
592 reg = <0x108000 0x1000>;
593 qcom,ipc = <&l2cc 0x8 2>;
595 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
598 interrupt-names = "ack",
602 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
605 #address-cells = <1>;
608 rpmcc: clock-controller {
609 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
614 compatible = "qcom,rpm-smb208-regulators";
617 regulator-min-microvolt = <1050000>;
618 regulator-max-microvolt = <1150000>;
620 qcom,switch-mode-frequency = <1200000>;
625 regulator-min-microvolt = <1050000>;
626 regulator-max-microvolt = <1150000>;
628 qcom,switch-mode-frequency = <1200000>;
632 regulator-min-microvolt = < 800000>;
633 regulator-max-microvolt = <1250000>;
635 qcom,switch-mode-frequency = <1200000>;
639 regulator-min-microvolt = < 800000>;
640 regulator-max-microvolt = <1250000>;
642 qcom,switch-mode-frequency = <1200000>;
648 compatible = "qcom,prng";
649 reg = <0x1a500000 0x200>;
650 clocks = <&gcc PRNG_CLK>;
651 clock-names = "core";
654 qcom_pinmux: pinmux@800000 {
655 compatible = "qcom,ipq8064-pinctrl";
656 reg = <0x800000 0x4000>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
662 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
664 pcie0_pins: pcie0_pinmux {
667 function = "pcie1_rst";
668 drive-strength = <12>;
673 pcie1_pins: pcie1_pinmux {
676 function = "pcie2_rst";
677 drive-strength = <12>;
682 pcie2_pins: pcie2_pinmux {
685 function = "pcie3_rst";
686 drive-strength = <12>;
694 pins = "gpio18", "gpio19", "gpio21";
696 drive-strength = <10>;
701 leds_pins: leds_pins {
703 pins = "gpio7", "gpio8", "gpio9",
706 drive-strength = <2>;
712 buttons_pins: buttons_pins {
715 drive-strength = <2>;
721 intc: interrupt-controller@2000000 {
722 compatible = "qcom,msm-qgic2";
723 interrupt-controller;
724 #interrupt-cells = <3>;
725 reg = <0x02000000 0x1000>,
730 compatible = "qcom,kpss-timer",
731 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
732 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
733 IRQ_TYPE_EDGE_RISING)>,
734 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
735 IRQ_TYPE_EDGE_RISING)>,
736 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
737 IRQ_TYPE_EDGE_RISING)>,
738 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
739 IRQ_TYPE_EDGE_RISING)>,
740 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
741 IRQ_TYPE_EDGE_RISING)>;
742 reg = <0x0200a000 0x100>;
743 clock-frequency = <25000000>,
745 clocks = <&sleep_clk>;
746 clock-names = "sleep";
747 cpu-offset = <0x80000>;
750 acpu0_aux: clock-controller@2088000 {
751 compatible = "qcom,kpss-acc-v1";
752 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
753 clock-output-names = "acpu0_aux";
756 acpu1_aux: clock-controller@2098000 {
757 compatible = "qcom,kpss-acc-v1";
758 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
759 clock-output-names = "acpu1_aux";
762 l2cc: clock-controller@2011000 {
763 compatible = "qcom,kpss-gcc", "syscon";
764 reg = <0x2011000 0x1000>;
765 clock-output-names = "acpu_l2_aux";
768 kraitcc: clock-controller {
769 compatible = "qcom,krait-cc-v1";
773 saw0: regulator@2089000 {
774 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
775 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
779 saw1: regulator@2099000 {
780 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
781 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
785 saw_l2: regulator@02012000 {
786 compatible = "qcom,saw2", "syscon";
787 reg = <0x02012000 0x1000>;
791 sic_non_secure: sic-non-secure@12100000 {
792 compatible = "syscon";
793 reg = <0x12100000 0x10000>;
796 gsbi2: gsbi@12480000 {
797 compatible = "qcom,gsbi-v1.0.0";
799 reg = <0x12480000 0x100>;
800 clocks = <&gcc GSBI2_H_CLK>;
801 clock-names = "iface";
802 #address-cells = <1>;
807 syscon-tcsr = <&tcsr>;
809 uart2: serial@12490000 {
810 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
811 reg = <0x12490000 0x1000>,
813 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
815 clock-names = "core", "iface";
820 compatible = "qcom,i2c-qup-v1.1.1";
821 reg = <0x124a0000 0x1000>;
822 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
825 clock-names = "core", "iface";
828 #address-cells = <1>;
834 gsbi4: gsbi@16300000 {
835 compatible = "qcom,gsbi-v1.0.0";
837 reg = <0x16300000 0x100>;
838 clocks = <&gcc GSBI4_H_CLK>;
839 clock-names = "iface";
840 #address-cells = <1>;
845 syscon-tcsr = <&tcsr>;
847 gsbi4_serial: serial@16340000 {
848 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
849 reg = <0x16340000 0x1000>,
851 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
853 clock-names = "core", "iface";
858 compatible = "qcom,i2c-qup-v1.1.1";
859 reg = <0x16380000 0x1000>;
860 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
863 clock-names = "core", "iface";
866 #address-cells = <1>;
871 gsbi5: gsbi@1a200000 {
872 compatible = "qcom,gsbi-v1.0.0";
874 reg = <0x1a200000 0x100>;
875 clocks = <&gcc GSBI5_H_CLK>;
876 clock-names = "iface";
877 #address-cells = <1>;
882 syscon-tcsr = <&tcsr>;
884 uart5: serial@1a240000 {
885 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
886 reg = <0x1a240000 0x1000>,
888 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
890 clock-names = "core", "iface";
895 compatible = "qcom,i2c-qup-v1.1.1";
896 reg = <0x1a280000 0x1000>;
897 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
900 clock-names = "core", "iface";
903 #address-cells = <1>;
908 compatible = "qcom,spi-qup-v1.1.1";
909 reg = <0x1a280000 0x1000>;
910 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
913 clock-names = "core", "iface";
916 #address-cells = <1>;
921 gsbi7: gsbi@16600000 {
923 compatible = "qcom,gsbi-v1.0.0";
925 reg = <0x16600000 0x100>;
926 clocks = <&gcc GSBI7_H_CLK>;
927 clock-names = "iface";
928 #address-cells = <1>;
931 syscon-tcsr = <&tcsr>;
933 gsbi7_serial: serial@16640000 {
934 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
935 reg = <0x16640000 0x1000>,
937 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
939 clock-names = "core", "iface";
944 sata_phy: sata-phy@1b400000 {
945 compatible = "qcom,ipq806x-sata-phy";
946 reg = <0x1b400000 0x200>;
948 clocks = <&gcc SATA_PHY_CFG_CLK>;
955 sata: sata@29000000 {
956 compatible = "qcom,ipq806x-ahci", "generic-ahci";
957 reg = <0x29000000 0x180>;
959 ports-implemented = <0x1>;
961 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&gcc SFAB_SATA_S_H_CLK>,
966 <&gcc SATA_RXOOB_CLK>,
967 <&gcc SATA_PMALIVE_CLK>;
968 clock-names = "slave_face", "iface", "core",
971 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
972 assigned-clock-rates = <100000000>, <100000000>;
975 phy-names = "sata-phy";
980 compatible = "qcom,ssbi";
981 reg = <0x00500000 0x1000>;
982 qcom,controller-type = "pmic-arbiter";
985 gcc: clock-controller@900000 {
986 compatible = "qcom,gcc-ipq8064";
987 reg = <0x00900000 0x4000>;
990 #power-domain-cells = <1>;
993 tsens: thermal-sensor@900000 {
994 compatible = "qcom,ipq8064-tsens";
995 reg = <0x900000 0x3680>;
996 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
997 nvmem-cell-names = "calib", "calib_backup";
998 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
999 #thermal-sensor-cells = <1>;
1002 tcsr: syscon@1a400000 {
1003 compatible = "qcom,tcsr-ipq8064", "syscon";
1004 reg = <0x1a400000 0x100>;
1007 lcc: clock-controller@28000000 {
1008 compatible = "qcom,lcc-ipq8064";
1009 reg = <0x28000000 0x1000>;
1014 sfpb_mutex_block: syscon@1200600 {
1015 compatible = "syscon";
1016 reg = <0x01200600 0x100>;
1019 hs_phy_0: hs_phy_0 {
1020 compatible = "qcom,dwc3-hs-usb-phy";
1022 clocks = <&gcc USB30_0_UTMI_CLK>;
1023 clock-names = "ref";
1027 ss_phy_0: ss_phy_0 {
1028 compatible = "qcom,dwc3-ss-usb-phy";
1030 clocks = <&gcc USB30_0_MASTER_CLK>;
1031 clock-names = "ref";
1035 usb3_0: usb3@110f8800 {
1036 compatible = "qcom,dwc3", "syscon";
1037 #address-cells = <1>;
1039 reg = <0x110f8800 0x8000>;
1040 clocks = <&gcc USB30_0_MASTER_CLK>;
1041 clock-names = "core";
1045 resets = <&gcc USB30_0_MASTER_RESET>;
1046 reset-names = "master";
1048 status = "disabled";
1050 dwc3_0: dwc3@11000000 {
1051 compatible = "snps,dwc3";
1052 reg = <0x11000000 0xcd00>;
1053 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1054 phys = <&hs_phy_0>, <&ss_phy_0>;
1055 phy-names = "usb2-phy", "usb3-phy";
1057 snps,dis_u3_susphy_quirk;
1061 hs_phy_1: hs_phy_1 {
1062 compatible = "qcom,dwc3-hs-usb-phy";
1064 clocks = <&gcc USB30_1_UTMI_CLK>;
1065 clock-names = "ref";
1069 ss_phy_1: ss_phy_1 {
1070 compatible = "qcom,dwc3-ss-usb-phy";
1072 clocks = <&gcc USB30_1_MASTER_CLK>;
1073 clock-names = "ref";
1077 usb3_1: usb3@100f8800 {
1078 compatible = "qcom,dwc3", "syscon";
1079 #address-cells = <1>;
1081 reg = <0x100f8800 0x8000>;
1082 clocks = <&gcc USB30_1_MASTER_CLK>;
1083 clock-names = "core";
1087 resets = <&gcc USB30_1_MASTER_RESET>;
1088 reset-names = "master";
1090 status = "disabled";
1092 dwc3_1: dwc3@10000000 {
1093 compatible = "snps,dwc3";
1094 reg = <0x10000000 0xcd00>;
1095 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1096 phys = <&hs_phy_1>, <&ss_phy_1>;
1097 phy-names = "usb2-phy", "usb3-phy";
1099 snps,dis_u3_susphy_quirk;
1103 pcie0: pci@1b500000 {
1104 compatible = "qcom,pcie-ipq8064";
1105 reg = <0x1b500000 0x1000
1108 0x0ff00000 0x100000>;
1109 reg-names = "dbi", "elbi", "parf", "config";
1110 device_type = "pci";
1111 linux,pci-domain = <0>;
1112 bus-range = <0x00 0xff>;
1114 #address-cells = <3>;
1117 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1118 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1120 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1121 interrupt-names = "msi";
1122 #interrupt-cells = <1>;
1123 interrupt-map-mask = <0 0 0 0x7>;
1124 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1125 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1126 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1127 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1129 clocks = <&gcc PCIE_A_CLK>,
1131 <&gcc PCIE_PHY_CLK>,
1132 <&gcc PCIE_AUX_CLK>,
1133 <&gcc PCIE_ALT_REF_CLK>;
1134 clock-names = "core", "iface", "phy", "aux", "ref";
1136 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1137 assigned-clock-rates = <100000000>;
1139 resets = <&gcc PCIE_ACLK_RESET>,
1140 <&gcc PCIE_HCLK_RESET>,
1141 <&gcc PCIE_POR_RESET>,
1142 <&gcc PCIE_PCI_RESET>,
1143 <&gcc PCIE_PHY_RESET>,
1144 <&gcc PCIE_EXT_RESET>;
1145 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1147 pinctrl-0 = <&pcie0_pins>;
1148 pinctrl-names = "default";
1150 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1152 phy-tx0-term-offset = <7>;
1154 status = "disabled";
1157 pcie1: pci@1b700000 {
1158 compatible = "qcom,pcie-ipq8064";
1159 reg = <0x1b700000 0x1000
1162 0x31f00000 0x100000>;
1163 reg-names = "dbi", "elbi", "parf", "config";
1164 device_type = "pci";
1165 linux,pci-domain = <1>;
1166 bus-range = <0x00 0xff>;
1168 #address-cells = <3>;
1171 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1172 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1174 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1175 interrupt-names = "msi";
1176 #interrupt-cells = <1>;
1177 interrupt-map-mask = <0 0 0 0x7>;
1178 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1179 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1180 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1181 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1183 clocks = <&gcc PCIE_1_A_CLK>,
1184 <&gcc PCIE_1_H_CLK>,
1185 <&gcc PCIE_1_PHY_CLK>,
1186 <&gcc PCIE_1_AUX_CLK>,
1187 <&gcc PCIE_1_ALT_REF_CLK>;
1188 clock-names = "core", "iface", "phy", "aux", "ref";
1190 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1191 assigned-clock-rates = <100000000>;
1193 resets = <&gcc PCIE_1_ACLK_RESET>,
1194 <&gcc PCIE_1_HCLK_RESET>,
1195 <&gcc PCIE_1_POR_RESET>,
1196 <&gcc PCIE_1_PCI_RESET>,
1197 <&gcc PCIE_1_PHY_RESET>,
1198 <&gcc PCIE_1_EXT_RESET>;
1199 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1201 pinctrl-0 = <&pcie1_pins>;
1202 pinctrl-names = "default";
1204 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1206 phy-tx0-term-offset = <7>;
1208 status = "disabled";
1211 pcie2: pci@1b900000 {
1212 compatible = "qcom,pcie-ipq8064";
1213 reg = <0x1b900000 0x1000
1216 0x35f00000 0x100000>;
1217 reg-names = "dbi", "elbi", "parf", "config";
1218 device_type = "pci";
1219 linux,pci-domain = <2>;
1220 bus-range = <0x00 0xff>;
1222 #address-cells = <3>;
1225 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1226 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1228 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1229 interrupt-names = "msi";
1230 #interrupt-cells = <1>;
1231 interrupt-map-mask = <0 0 0 0x7>;
1232 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1233 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1234 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1235 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1237 clocks = <&gcc PCIE_2_A_CLK>,
1238 <&gcc PCIE_2_H_CLK>,
1239 <&gcc PCIE_2_PHY_CLK>,
1240 <&gcc PCIE_2_AUX_CLK>,
1241 <&gcc PCIE_2_ALT_REF_CLK>;
1242 clock-names = "core", "iface", "phy", "aux", "ref";
1244 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1245 assigned-clock-rates = <100000000>;
1247 resets = <&gcc PCIE_2_ACLK_RESET>,
1248 <&gcc PCIE_2_HCLK_RESET>,
1249 <&gcc PCIE_2_POR_RESET>,
1250 <&gcc PCIE_2_PCI_RESET>,
1251 <&gcc PCIE_2_PHY_RESET>,
1252 <&gcc PCIE_2_EXT_RESET>;
1253 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1255 pinctrl-0 = <&pcie2_pins>;
1256 pinctrl-names = "default";
1258 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1260 phy-tx0-term-offset = <7>;
1262 status = "disabled";
1265 adm_dma: dma@18300000 {
1266 compatible = "qcom,adm";
1267 reg = <0x18300000 0x100000>;
1268 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1272 clock-names = "core", "iface";
1274 resets = <&gcc ADM0_RESET>,
1275 <&gcc ADM0_PBUS_RESET>,
1276 <&gcc ADM0_C0_RESET>,
1277 <&gcc ADM0_C1_RESET>,
1278 <&gcc ADM0_C2_RESET>;
1279 reset-names = "clk", "pbus", "c0", "c1", "c2";
1282 status = "disabled";
1285 nand: nand@1ac00000 {
1286 compatible = "qcom,ipq806x-nand";
1287 reg = <0x1ac00000 0x800>;
1289 clocks = <&gcc EBI2_CLK>,
1290 <&gcc EBI2_AON_CLK>;
1291 clock-names = "core", "aon";
1293 dmas = <&adm_dma 3>;
1295 qcom,cmd-crci = <15>;
1296 qcom,data-crci = <3>;
1298 status = "disabled";
1300 #address-cells = <1>;
1304 nss_common: syscon@03000000 {
1305 compatible = "syscon";
1306 reg = <0x03000000 0x0000FFFF>;
1309 qsgmii_csr: syscon@1bb00000 {
1310 compatible = "syscon";
1311 reg = <0x1bb00000 0x000001FF>;
1314 stmmac_axi_setup: stmmac-axi-config {
1315 snps,wr_osr_lmt = <7>;
1316 snps,rd_osr_lmt = <7>;
1317 snps,blen = <16 0 0 0 0 0 0>;
1320 gmac0: ethernet@37000000 {
1321 device_type = "network";
1322 compatible = "qcom,ipq806x-gmac";
1323 reg = <0x37000000 0x200000>;
1324 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1325 interrupt-names = "macirq";
1327 snps,axi-config = <&stmmac_axi_setup>;
1331 qcom,nss-common = <&nss_common>;
1332 qcom,qsgmii-csr = <&qsgmii_csr>;
1334 clocks = <&gcc GMAC_CORE1_CLK>;
1335 clock-names = "stmmaceth";
1337 resets = <&gcc GMAC_CORE1_RESET>;
1338 reset-names = "stmmaceth";
1340 status = "disabled";
1343 gmac1: ethernet@37200000 {
1344 device_type = "network";
1345 compatible = "qcom,ipq806x-gmac";
1346 reg = <0x37200000 0x200000>;
1347 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1348 interrupt-names = "macirq";
1350 snps,axi-config = <&stmmac_axi_setup>;
1354 qcom,nss-common = <&nss_common>;
1355 qcom,qsgmii-csr = <&qsgmii_csr>;
1357 clocks = <&gcc GMAC_CORE2_CLK>;
1358 clock-names = "stmmaceth";
1360 resets = <&gcc GMAC_CORE2_RESET>;
1361 reset-names = "stmmaceth";
1363 status = "disabled";
1366 gmac2: ethernet@37400000 {
1367 device_type = "network";
1368 compatible = "qcom,ipq806x-gmac";
1369 reg = <0x37400000 0x200000>;
1370 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1371 interrupt-names = "macirq";
1373 snps,axi-config = <&stmmac_axi_setup>;
1377 qcom,nss-common = <&nss_common>;
1378 qcom,qsgmii-csr = <&qsgmii_csr>;
1380 clocks = <&gcc GMAC_CORE3_CLK>;
1381 clock-names = "stmmaceth";
1383 resets = <&gcc GMAC_CORE3_RESET>;
1384 reset-names = "stmmaceth";
1386 status = "disabled";
1389 gmac3: ethernet@37600000 {
1390 device_type = "network";
1391 compatible = "qcom,ipq806x-gmac";
1392 reg = <0x37600000 0x200000>;
1393 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1394 interrupt-names = "macirq";
1396 snps,axi-config = <&stmmac_axi_setup>;
1400 qcom,nss-common = <&nss_common>;
1401 qcom,qsgmii-csr = <&qsgmii_csr>;
1403 clocks = <&gcc GMAC_CORE4_CLK>;
1404 clock-names = "stmmaceth";
1406 resets = <&gcc GMAC_CORE4_RESET>;
1407 reset-names = "stmmaceth";
1409 status = "disabled";
1412 /* Temporary fixed regulator */
1413 vsdcc_fixed: vsdcc-regulator {
1414 compatible = "regulator-fixed";
1415 regulator-name = "SDCC Power";
1416 regulator-min-microvolt = <3300000>;
1417 regulator-max-microvolt = <3300000>;
1418 regulator-always-on;
1421 sdcc1bam:dma@12402000 {
1422 compatible = "qcom,bam-v1.3.0";
1423 reg = <0x12402000 0x8000>;
1424 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&gcc SDC1_H_CLK>;
1426 clock-names = "bam_clk";
1431 sdcc3bam:dma@12182000 {
1432 compatible = "qcom,bam-v1.3.0";
1433 reg = <0x12182000 0x8000>;
1434 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1435 clocks = <&gcc SDC3_H_CLK>;
1436 clock-names = "bam_clk";
1442 compatible = "arm,amba-bus";
1443 #address-cells = <1>;
1446 sdcc1: sdcc@12400000 {
1447 status = "disabled";
1448 compatible = "arm,pl18x", "arm,primecell";
1449 arm,primecell-periphid = <0x00051180>;
1450 reg = <0x12400000 0x2000>;
1451 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1452 interrupt-names = "cmd_irq";
1453 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1454 clock-names = "mclk", "apb_pclk";
1456 max-frequency = <96000000>;
1460 vmmc-supply = <&vsdcc_fixed>;
1461 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1462 dma-names = "tx", "rx";
1465 sdcc3: sdcc@12180000 {
1466 compatible = "arm,pl18x", "arm,primecell";
1467 arm,primecell-periphid = <0x00051180>;
1468 status = "disabled";
1469 reg = <0x12180000 0x2000>;
1470 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1471 interrupt-names = "cmd_irq";
1472 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1473 clock-names = "mclk", "apb_pclk";
1477 max-frequency = <192000000>;
1481 vqmmc-supply = <&vsdcc_fixed>;
1482 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1483 dma-names = "tx", "rx";
1488 sfpb_mutex: sfpb-mutex {
1489 compatible = "qcom,sfpb-mutex";
1490 syscon = <&sfpb_mutex_block 4 4>;
1492 #hwlock-cells = <1>;
1496 compatible = "qcom,smem";
1497 memory-region = <&smem>;
1498 hwlocks = <&sfpb_mutex 3>;