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[openwrt/staging/stintel.git] / target / linux / ipq806x / files-4.19 / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acc0>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 voltage-tolerance = <5>;
35 cooling-min-state = <0>;
36 cooling-max-state = <10>;
37 #cooling-cells = <2>;
38 cpu-idle-states = <&CPU_SPC>;
39 };
40
41 cpu1: cpu@1 {
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
44 device_type = "cpu";
45 reg = <1>;
46 next-level-cache = <&L2>;
47 qcom,acc = <&acc1>;
48 qcom,saw = <&saw1>;
49 clocks = <&kraitcc 1>, <&kraitcc 4>;
50 clock-names = "cpu", "l2";
51 clock-latency = <100000>;
52 cpu-supply = <&smb208_s2b>;
53 cooling-min-state = <0>;
54 cooling-max-state = <10>;
55 #cooling-cells = <2>;
56 cpu-idle-states = <&CPU_SPC>;
57 };
58
59 L2: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 qcom,saw = <&saw_l2>;
63 };
64
65 qcom,l2 {
66 qcom,l2-rates = <384000000 1000000000 1200000000>;
67 };
68
69 idle-states {
70 CPU_SPC: spc {
71 compatible = "qcom,idle-state-spc",
72 "arm,idle-state";
73 entry-latency-us = <400>;
74 exit-latency-us = <900>;
75 min-residency-us = <3000>;
76 };
77 };
78 };
79
80 thermal-zones {
81 tsens_tz_sensor0 {
82 polling-delay-passive = <0>;
83 polling-delay = <0>;
84 thermal-sensors = <&tsens 0>;
85
86 trips {
87 cpu-critical-hi {
88 temperature = <125000>;
89 hysteresis = <2000>;
90 type = "critical_high";
91 };
92
93 cpu-config-hi {
94 temperature = <105000>;
95 hysteresis = <2000>;
96 type = "configurable_hi";
97 };
98
99 cpu-config-lo {
100 temperature = <95000>;
101 hysteresis = <2000>;
102 type = "configurable_lo";
103 };
104
105 cpu-critical-low {
106 temperature = <0>;
107 hysteresis = <2000>;
108 type = "critical_low";
109 };
110 };
111 };
112
113 tsens_tz_sensor1 {
114 polling-delay-passive = <0>;
115 polling-delay = <0>;
116 thermal-sensors = <&tsens 1>;
117
118 trips {
119 cpu-critical-hi {
120 temperature = <125000>;
121 hysteresis = <2000>;
122 type = "critical_high";
123 };
124
125 cpu-config-hi {
126 temperature = <105000>;
127 hysteresis = <2000>;
128 type = "configurable_hi";
129 };
130
131 cpu-config-lo {
132 temperature = <95000>;
133 hysteresis = <2000>;
134 type = "configurable_lo";
135 };
136
137 cpu-critical-low {
138 temperature = <0>;
139 hysteresis = <2000>;
140 type = "critical_low";
141 };
142 };
143 };
144
145 tsens_tz_sensor2 {
146 polling-delay-passive = <0>;
147 polling-delay = <0>;
148 thermal-sensors = <&tsens 2>;
149
150 trips {
151 cpu-critical-hi {
152 temperature = <125000>;
153 hysteresis = <2000>;
154 type = "critical_high";
155 };
156
157 cpu-config-hi {
158 temperature = <105000>;
159 hysteresis = <2000>;
160 type = "configurable_hi";
161 };
162
163 cpu-config-lo {
164 temperature = <95000>;
165 hysteresis = <2000>;
166 type = "configurable_lo";
167 };
168
169 cpu-critical-low {
170 temperature = <0>;
171 hysteresis = <2000>;
172 type = "critical_low";
173 };
174 };
175 };
176
177 tsens_tz_sensor3 {
178 polling-delay-passive = <0>;
179 polling-delay = <0>;
180 thermal-sensors = <&tsens 3>;
181
182 trips {
183 cpu-critical-hi {
184 temperature = <125000>;
185 hysteresis = <2000>;
186 type = "critical_high";
187 };
188
189 cpu-config-hi {
190 temperature = <105000>;
191 hysteresis = <2000>;
192 type = "configurable_hi";
193 };
194
195 cpu-config-lo {
196 temperature = <95000>;
197 hysteresis = <2000>;
198 type = "configurable_lo";
199 };
200
201 cpu-critical-low {
202 temperature = <0>;
203 hysteresis = <2000>;
204 type = "critical_low";
205 };
206 };
207 };
208
209 tsens_tz_sensor4 {
210 polling-delay-passive = <0>;
211 polling-delay = <0>;
212 thermal-sensors = <&tsens 4>;
213
214 trips {
215 cpu-critical-hi {
216 temperature = <125000>;
217 hysteresis = <2000>;
218 type = "critical_high";
219 };
220
221 cpu-config-hi {
222 temperature = <105000>;
223 hysteresis = <2000>;
224 type = "configurable_hi";
225 };
226
227 cpu-config-lo {
228 temperature = <95000>;
229 hysteresis = <2000>;
230 type = "configurable_lo";
231 };
232
233 cpu-critical-low {
234 temperature = <0>;
235 hysteresis = <2000>;
236 type = "critical_low";
237 };
238 };
239 };
240
241 tsens_tz_sensor5 {
242 polling-delay-passive = <0>;
243 polling-delay = <0>;
244 thermal-sensors = <&tsens 5>;
245
246 trips {
247 cpu-critical-hi {
248 temperature = <125000>;
249 hysteresis = <2000>;
250 type = "critical_high";
251 };
252
253 cpu-config-hi {
254 temperature = <105000>;
255 hysteresis = <2000>;
256 type = "configurable_hi";
257 };
258
259 cpu-config-lo {
260 temperature = <95000>;
261 hysteresis = <2000>;
262 type = "configurable_lo";
263 };
264
265 cpu-critical-low {
266 temperature = <0>;
267 hysteresis = <2000>;
268 type = "critical_low";
269 };
270 };
271 };
272
273 tsens_tz_sensor6 {
274 polling-delay-passive = <0>;
275 polling-delay = <0>;
276 thermal-sensors = <&tsens 6>;
277
278 trips {
279 cpu-critical-hi {
280 temperature = <125000>;
281 hysteresis = <2000>;
282 type = "critical_high";
283 };
284
285 cpu-config-hi {
286 temperature = <105000>;
287 hysteresis = <2000>;
288 type = "configurable_hi";
289 };
290
291 cpu-config-lo {
292 temperature = <95000>;
293 hysteresis = <2000>;
294 type = "configurable_lo";
295 };
296
297 cpu-critical-low {
298 temperature = <0>;
299 hysteresis = <2000>;
300 type = "critical_low";
301 };
302 };
303 };
304
305 tsens_tz_sensor7 {
306 polling-delay-passive = <0>;
307 polling-delay = <0>;
308 thermal-sensors = <&tsens 7>;
309
310 trips {
311 cpu-critical-hi {
312 temperature = <125000>;
313 hysteresis = <2000>;
314 type = "critical_high";
315 };
316
317 cpu-config-hi {
318 temperature = <105000>;
319 hysteresis = <2000>;
320 type = "configurable_hi";
321 };
322
323 cpu-config-lo {
324 temperature = <95000>;
325 hysteresis = <2000>;
326 type = "configurable_lo";
327 };
328
329 cpu-critical-low {
330 temperature = <0>;
331 hysteresis = <2000>;
332 type = "critical_low";
333 };
334 };
335 };
336
337 tsens_tz_sensor8 {
338 polling-delay-passive = <0>;
339 polling-delay = <0>;
340 thermal-sensors = <&tsens 8>;
341
342 trips {
343 cpu-critical-hi {
344 temperature = <125000>;
345 hysteresis = <2000>;
346 type = "critical_high";
347 };
348
349 cpu-config-hi {
350 temperature = <105000>;
351 hysteresis = <2000>;
352 type = "configurable_hi";
353 };
354
355 cpu-config-lo {
356 temperature = <95000>;
357 hysteresis = <2000>;
358 type = "configurable_lo";
359 };
360
361 cpu-critical-low {
362 temperature = <0>;
363 hysteresis = <2000>;
364 type = "critical_low";
365 };
366 };
367 };
368
369 tsens_tz_sensor9 {
370 polling-delay-passive = <0>;
371 polling-delay = <0>;
372 thermal-sensors = <&tsens 9>;
373
374 trips {
375 cpu-critical-hi {
376 temperature = <125000>;
377 hysteresis = <2000>;
378 type = "critical_high";
379 };
380
381 cpu-config-hi {
382 temperature = <105000>;
383 hysteresis = <2000>;
384 type = "configurable_hi";
385 };
386
387 cpu-config-lo {
388 temperature = <95000>;
389 hysteresis = <2000>;
390 type = "configurable_lo";
391 };
392
393 cpu-critical-low {
394 temperature = <0>;
395 hysteresis = <2000>;
396 type = "critical_low";
397 };
398 };
399 };
400
401 tsens_tz_sensor10 {
402 polling-delay-passive = <0>;
403 polling-delay = <0>;
404 thermal-sensors = <&tsens 10>;
405
406 trips {
407 cpu-critical-hi {
408 temperature = <125000>;
409 hysteresis = <2000>;
410 type = "critical_high";
411 };
412
413 cpu-config-hi {
414 temperature = <105000>;
415 hysteresis = <2000>;
416 type = "configurable_hi";
417 };
418
419 cpu-config-lo {
420 temperature = <95000>;
421 hysteresis = <2000>;
422 type = "configurable_lo";
423 };
424
425 cpu-critical-low {
426 temperature = <0>;
427 hysteresis = <2000>;
428 type = "critical_low";
429 };
430 };
431 };
432 };
433
434 cpu-pmu {
435 compatible = "qcom,krait-pmu";
436 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
437 IRQ_TYPE_LEVEL_HIGH)>;
438 };
439
440 reserved-memory {
441 #address-cells = <1>;
442 #size-cells = <1>;
443 ranges;
444
445 nss@40000000 {
446 reg = <0x40000000 0x1000000>;
447 no-map;
448 };
449
450 smem: smem@41000000 {
451 reg = <0x41000000 0x200000>;
452 no-map;
453 };
454 };
455
456 clocks {
457 cxo_board {
458 compatible = "fixed-clock";
459 #clock-cells = <0>;
460 clock-frequency = <25000000>;
461 };
462
463 pxo_board {
464 compatible = "fixed-clock";
465 #clock-cells = <0>;
466 clock-frequency = <25000000>;
467 };
468
469 sleep_clk: sleep_clk {
470 compatible = "fixed-clock";
471 clock-frequency = <32768>;
472 #clock-cells = <0>;
473 };
474 };
475
476 firmware {
477 scm {
478 compatible = "qcom,scm-ipq806x";
479 };
480 };
481
482 kraitcc: clock-controller {
483 compatible = "qcom,krait-cc-v1";
484 #clock-cells = <1>;
485 };
486
487 qcom,pvs {
488 qcom,pvs-format-a;
489 qcom,speed0-pvs0-bin-v0 =
490 < 1400000000 1250000 >,
491 < 1200000000 1200000 >,
492 < 1000000000 1150000 >,
493 < 800000000 1100000 >,
494 < 600000000 1050000 >,
495 < 384000000 1000000 >;
496
497 qcom,speed0-pvs1-bin-v0 =
498 < 1400000000 1175000 >,
499 < 1200000000 1125000 >,
500 < 1000000000 1075000 >,
501 < 800000000 1025000 >,
502 < 600000000 975000 >,
503 < 384000000 925000 >;
504
505 qcom,speed0-pvs2-bin-v0 =
506 < 1400000000 1125000 >,
507 < 1200000000 1075000 >,
508 < 1000000000 1025000 >,
509 < 800000000 995000 >,
510 < 600000000 925000 >,
511 < 384000000 875000 >;
512
513 qcom,speed0-pvs3-bin-v0 =
514 < 1400000000 1050000 >,
515 < 1200000000 1000000 >,
516 < 1000000000 950000 >,
517 < 800000000 900000 >,
518 < 600000000 850000 >,
519 < 384000000 800000 >;
520 };
521
522 soc: soc {
523 #address-cells = <1>;
524 #size-cells = <1>;
525 ranges;
526 compatible = "simple-bus";
527
528 lpass@28100000 {
529 compatible = "qcom,lpass-cpu";
530 status = "disabled";
531 clocks = <&lcc AHBIX_CLK>,
532 <&lcc MI2S_OSR_CLK>,
533 <&lcc MI2S_BIT_CLK>;
534 clock-names = "ahbix-clk",
535 "mi2s-osr-clk",
536 "mi2s-bit-clk";
537 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
538 interrupt-names = "lpass-irq-lpaif";
539 reg = <0x28100000 0x10000>;
540 reg-names = "lpass-lpaif";
541 };
542
543 qfprom: qfprom@700000 {
544 compatible = "qcom,qfprom", "syscon";
545 reg = <0x700000 0x1000>;
546 #address-cells = <1>;
547 #size-cells = <1>;
548 status = "okay";
549 tsens_calib: calib@400 {
550 reg = <0x400 0x10>;
551 };
552 tsens_backup: backup@410 {
553 reg = <0x410 0x10>;
554 };
555 };
556
557 rpm@108000 {
558 compatible = "qcom,rpm-ipq8064";
559 reg = <0x108000 0x1000>;
560 qcom,ipc = <&l2cc 0x8 2>;
561
562 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
565 interrupt-names = "ack",
566 "err",
567 "wakeup";
568
569 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
570 clock-names = "ram";
571
572 #address-cells = <1>;
573 #size-cells = <0>;
574
575 rpmcc: clock-controller {
576 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
577 #clock-cells = <1>;
578 };
579
580 regulators {
581 compatible = "qcom,rpm-smb208-regulators";
582
583 smb208_s1a: s1a {
584 regulator-min-microvolt = <1050000>;
585 regulator-max-microvolt = <1150000>;
586
587 qcom,switch-mode-frequency = <1200000>;
588
589 };
590
591 smb208_s1b: s1b {
592 regulator-min-microvolt = <1050000>;
593 regulator-max-microvolt = <1150000>;
594
595 qcom,switch-mode-frequency = <1200000>;
596 };
597
598 smb208_s2a: s2a {
599 regulator-min-microvolt = < 800000>;
600 regulator-max-microvolt = <1250000>;
601
602 qcom,switch-mode-frequency = <1200000>;
603 };
604
605 smb208_s2b: s2b {
606 regulator-min-microvolt = < 800000>;
607 regulator-max-microvolt = <1250000>;
608
609 qcom,switch-mode-frequency = <1200000>;
610 };
611 };
612 };
613
614 rng@1a500000 {
615 compatible = "qcom,prng";
616 reg = <0x1a500000 0x200>;
617 clocks = <&gcc PRNG_CLK>;
618 clock-names = "core";
619 };
620
621 qcom_pinmux: pinmux@800000 {
622 compatible = "qcom,ipq8064-pinctrl";
623 reg = <0x800000 0x4000>;
624
625 gpio-controller;
626 #gpio-cells = <2>;
627 interrupt-controller;
628 #interrupt-cells = <2>;
629 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
630
631 pcie0_pins: pcie0_pinmux {
632 mux {
633 pins = "gpio3";
634 function = "pcie1_rst";
635 drive-strength = <2>;
636 bias-disable;
637 };
638 };
639
640 pcie1_pins: pcie1_pinmux {
641 mux {
642 pins = "gpio48";
643 function = "pcie2_rst";
644 drive-strength = <2>;
645 bias-disable;
646 };
647 };
648
649 pcie2_pins: pcie2_pinmux {
650 mux {
651 pins = "gpio63";
652 function = "pcie3_rst";
653 drive-strength = <2>;
654 bias-disable;
655 output-low;
656 };
657 };
658 };
659
660 intc: interrupt-controller@2000000 {
661 compatible = "qcom,msm-qgic2";
662 interrupt-controller;
663 #interrupt-cells = <3>;
664 reg = <0x02000000 0x1000>,
665 <0x02002000 0x1000>;
666 };
667
668 timer@200a000 {
669 compatible = "qcom,kpss-timer", "qcom,msm-timer";
670 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
671 IRQ_TYPE_EDGE_RISING)>,
672 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
673 IRQ_TYPE_EDGE_RISING)>,
674 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
675 IRQ_TYPE_EDGE_RISING)>,
676 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
677 IRQ_TYPE_EDGE_RISING)>,
678 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
679 IRQ_TYPE_EDGE_RISING)>;
680 reg = <0x0200a000 0x100>;
681 clock-frequency = <25000000>,
682 <32768>;
683 clocks = <&sleep_clk>;
684 clock-names = "sleep";
685 cpu-offset = <0x80000>;
686 };
687
688 acc0: clock-controller@2088000 {
689 compatible = "qcom,kpss-acc-v1";
690 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
691 clock-output-names = "acpu0_aux";
692 };
693
694 acc1: clock-controller@2098000 {
695 compatible = "qcom,kpss-acc-v1";
696 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
697 clock-output-names = "acpu1_aux";
698 };
699
700 l2cc: clock-controller@2011000 {
701 compatible = "qcom,kpss-gcc", "syscon";
702 reg = <0x2011000 0x1000>;
703 clock-output-names = "acpu_l2_aux";
704 };
705
706 saw0: regulator@2089000 {
707 compatible = "qcom,saw2", "syscon";
708 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
709 regulator;
710 };
711
712 saw1: regulator@2099000 {
713 compatible = "qcom,saw2", "syscon";
714 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
715 regulator;
716 };
717
718 saw_l2: regulator@02012000 {
719 compatible = "qcom,saw2", "syscon";
720 reg = <0x02012000 0x1000>;
721 regulator;
722 };
723
724 sic_non_secure: sic-non-secure@12100000 {
725 compatible = "syscon";
726 reg = <0x12100000 0x10000>;
727 };
728
729 gsbi2: gsbi@12480000 {
730 compatible = "qcom,gsbi-v1.0.0";
731 cell-index = <2>;
732 reg = <0x12480000 0x100>;
733 clocks = <&gcc GSBI2_H_CLK>;
734 clock-names = "iface";
735 #address-cells = <1>;
736 #size-cells = <1>;
737 ranges;
738 status = "disabled";
739
740 syscon-tcsr = <&tcsr>;
741
742 uart2: serial@12490000 {
743 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
744 reg = <0x12490000 0x1000>,
745 <0x12480000 0x1000>;
746 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
748 clock-names = "core", "iface";
749 status = "disabled";
750 };
751
752 i2c@124a0000 {
753 compatible = "qcom,i2c-qup-v1.1.1";
754 reg = <0x124a0000 0x1000>;
755 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
756
757 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
758 clock-names = "core", "iface";
759 status = "disabled";
760
761 #address-cells = <1>;
762 #size-cells = <0>;
763 };
764
765 };
766
767 gsbi4: gsbi@16300000 {
768 compatible = "qcom,gsbi-v1.0.0";
769 cell-index = <4>;
770 reg = <0x16300000 0x100>;
771 clocks = <&gcc GSBI4_H_CLK>;
772 clock-names = "iface";
773 #address-cells = <1>;
774 #size-cells = <1>;
775 ranges;
776 status = "disabled";
777
778 syscon-tcsr = <&tcsr>;
779
780 gsbi4_serial: serial@16340000 {
781 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
782 reg = <0x16340000 0x1000>,
783 <0x16300000 0x1000>;
784 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
786 clock-names = "core", "iface";
787 status = "disabled";
788 };
789
790 i2c@16380000 {
791 compatible = "qcom,i2c-qup-v1.1.1";
792 reg = <0x16380000 0x1000>;
793 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
794
795 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
796 clock-names = "core", "iface";
797 status = "disabled";
798
799 #address-cells = <1>;
800 #size-cells = <0>;
801 };
802 };
803
804 gsbi5: gsbi@1a200000 {
805 compatible = "qcom,gsbi-v1.0.0";
806 cell-index = <5>;
807 reg = <0x1a200000 0x100>;
808 clocks = <&gcc GSBI5_H_CLK>;
809 clock-names = "iface";
810 #address-cells = <1>;
811 #size-cells = <1>;
812 ranges;
813 status = "disabled";
814
815 syscon-tcsr = <&tcsr>;
816
817 uart5: serial@1a240000 {
818 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
819 reg = <0x1a240000 0x1000>,
820 <0x1a200000 0x1000>;
821 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
823 clock-names = "core", "iface";
824 status = "disabled";
825 };
826
827 i2c@1a280000 {
828 compatible = "qcom,i2c-qup-v1.1.1";
829 reg = <0x1a280000 0x1000>;
830 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
831
832 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
833 clock-names = "core", "iface";
834 status = "disabled";
835
836 #address-cells = <1>;
837 #size-cells = <0>;
838 };
839
840 spi@1a280000 {
841 compatible = "qcom,spi-qup-v1.1.1";
842 reg = <0x1a280000 0x1000>;
843 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
844
845 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
846 clock-names = "core", "iface";
847 status = "disabled";
848
849 #address-cells = <1>;
850 #size-cells = <0>;
851 };
852 };
853
854 sata_phy: sata-phy@1b400000 {
855 compatible = "qcom,ipq806x-sata-phy";
856 reg = <0x1b400000 0x200>;
857
858 clocks = <&gcc SATA_PHY_CFG_CLK>;
859 clock-names = "cfg";
860
861 #phy-cells = <0>;
862 status = "disabled";
863 };
864
865 sata@29000000 {
866 compatible = "qcom,ipq806x-ahci", "generic-ahci";
867 reg = <0x29000000 0x180>;
868
869 ports-implemented = <0x1>;
870
871 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
872
873 clocks = <&gcc SFAB_SATA_S_H_CLK>,
874 <&gcc SATA_H_CLK>,
875 <&gcc SATA_A_CLK>,
876 <&gcc SATA_RXOOB_CLK>,
877 <&gcc SATA_PMALIVE_CLK>;
878 clock-names = "slave_face", "iface", "core",
879 "rxoob", "pmalive";
880
881 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
882 assigned-clock-rates = <100000000>, <100000000>;
883
884 phys = <&sata_phy>;
885 phy-names = "sata-phy";
886 status = "disabled";
887 };
888
889 qcom,ssbi@500000 {
890 compatible = "qcom,ssbi";
891 reg = <0x00500000 0x1000>;
892 qcom,controller-type = "pmic-arbiter";
893 };
894
895 gcc: clock-controller@900000 {
896 compatible = "qcom,gcc-ipq8064";
897 reg = <0x00900000 0x4000>;
898 #clock-cells = <1>;
899 #reset-cells = <1>;
900 #power-domain-cells = <1>;
901 };
902
903 tsens: thermal-sensor@900000 {
904 compatible = "qcom,ipq8064-tsens";
905 reg = <0x900000 0x3680>;
906 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
907 nvmem-cell-names = "calib", "calib_backup";
908 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
909 #thermal-sensor-cells = <1>;
910 };
911
912 tcsr: syscon@1a400000 {
913 compatible = "qcom,tcsr-ipq8064", "syscon";
914 reg = <0x1a400000 0x100>;
915 };
916
917 lcc: clock-controller@28000000 {
918 compatible = "qcom,lcc-ipq8064";
919 reg = <0x28000000 0x1000>;
920 #clock-cells = <1>;
921 #reset-cells = <1>;
922 };
923
924 sfpb_mutex_block: syscon@1200600 {
925 compatible = "syscon";
926 reg = <0x01200600 0x100>;
927 };
928
929 hs_phy_0: hs_phy_0 {
930 compatible = "qcom,dwc3-hs-usb-phy";
931 regmap = <&usb3_0>;
932 clocks = <&gcc USB30_0_UTMI_CLK>;
933 clock-names = "ref";
934 #phy-cells = <0>;
935 };
936
937 ss_phy_0: ss_phy_0 {
938 compatible = "qcom,dwc3-ss-usb-phy";
939 regmap = <&usb3_0>;
940 clocks = <&gcc USB30_0_MASTER_CLK>;
941 clock-names = "ref";
942 #phy-cells = <0>;
943 };
944
945 usb3_0: usb3@110f8800 {
946 compatible = "qcom,dwc3", "syscon";
947 #address-cells = <1>;
948 #size-cells = <1>;
949 reg = <0x110f8800 0x8000>;
950 clocks = <&gcc USB30_0_MASTER_CLK>;
951 clock-names = "core";
952
953 ranges;
954
955 resets = <&gcc USB30_0_MASTER_RESET>;
956 reset-names = "master";
957
958 status = "disabled";
959
960 dwc3_0: dwc3@11000000 {
961 compatible = "snps,dwc3";
962 reg = <0x11000000 0xcd00>;
963 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
964 phys = <&hs_phy_0>, <&ss_phy_0>;
965 phy-names = "usb2-phy", "usb3-phy";
966 dr_mode = "host";
967 snps,dis_u3_susphy_quirk;
968 };
969 };
970
971 hs_phy_1: hs_phy_1 {
972 compatible = "qcom,dwc3-hs-usb-phy";
973 regmap = <&usb3_1>;
974 clocks = <&gcc USB30_1_UTMI_CLK>;
975 clock-names = "ref";
976 #phy-cells = <0>;
977 };
978
979 ss_phy_1: ss_phy_1 {
980 compatible = "qcom,dwc3-ss-usb-phy";
981 regmap = <&usb3_1>;
982 clocks = <&gcc USB30_1_MASTER_CLK>;
983 clock-names = "ref";
984 #phy-cells = <0>;
985 };
986
987 usb3_1: usb3@100f8800 {
988 compatible = "qcom,dwc3", "syscon";
989 #address-cells = <1>;
990 #size-cells = <1>;
991 reg = <0x100f8800 0x8000>;
992 clocks = <&gcc USB30_1_MASTER_CLK>;
993 clock-names = "core";
994
995 ranges;
996
997 resets = <&gcc USB30_1_MASTER_RESET>;
998 reset-names = "master";
999
1000 status = "disabled";
1001
1002 dwc3_1: dwc3@10000000 {
1003 compatible = "snps,dwc3";
1004 reg = <0x10000000 0xcd00>;
1005 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1006 phys = <&hs_phy_1>, <&ss_phy_1>;
1007 phy-names = "usb2-phy", "usb3-phy";
1008 dr_mode = "host";
1009 snps,dis_u3_susphy_quirk;
1010 };
1011 };
1012
1013 pcie0: pci@1b500000 {
1014 compatible = "qcom,pcie-ipq8064";
1015 reg = <0x1b500000 0x1000
1016 0x1b502000 0x80
1017 0x1b600000 0x100
1018 0x0ff00000 0x100000>;
1019 reg-names = "dbi", "elbi", "parf", "config";
1020 device_type = "pci";
1021 linux,pci-domain = <0>;
1022 bus-range = <0x00 0xff>;
1023 num-lanes = <1>;
1024 #address-cells = <3>;
1025 #size-cells = <2>;
1026
1027 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1028 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1029
1030 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1031 interrupt-names = "msi";
1032 #interrupt-cells = <1>;
1033 interrupt-map-mask = <0 0 0 0x7>;
1034 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1035 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1036 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1037 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1038
1039 clocks = <&gcc PCIE_A_CLK>,
1040 <&gcc PCIE_H_CLK>,
1041 <&gcc PCIE_PHY_CLK>,
1042 <&gcc PCIE_AUX_CLK>,
1043 <&gcc PCIE_ALT_REF_CLK>;
1044 clock-names = "core", "iface", "phy", "aux", "ref";
1045
1046 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1047 assigned-clock-rates = <100000000>;
1048
1049 resets = <&gcc PCIE_ACLK_RESET>,
1050 <&gcc PCIE_HCLK_RESET>,
1051 <&gcc PCIE_POR_RESET>,
1052 <&gcc PCIE_PCI_RESET>,
1053 <&gcc PCIE_PHY_RESET>,
1054 <&gcc PCIE_EXT_RESET>;
1055 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1056
1057 pinctrl-0 = <&pcie0_pins>;
1058 pinctrl-names = "default";
1059
1060 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1061
1062 phy-tx0-term-offset = <7>;
1063
1064 status = "disabled";
1065 };
1066
1067 pcie1: pci@1b700000 {
1068 compatible = "qcom,pcie-ipq8064";
1069 reg = <0x1b700000 0x1000
1070 0x1b702000 0x80
1071 0x1b800000 0x100
1072 0x31f00000 0x100000>;
1073 reg-names = "dbi", "elbi", "parf", "config";
1074 device_type = "pci";
1075 linux,pci-domain = <1>;
1076 bus-range = <0x00 0xff>;
1077 num-lanes = <1>;
1078 #address-cells = <3>;
1079 #size-cells = <2>;
1080
1081 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1082 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1083
1084 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1085 interrupt-names = "msi";
1086 #interrupt-cells = <1>;
1087 interrupt-map-mask = <0 0 0 0x7>;
1088 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1089 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1090 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1091 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1092
1093 clocks = <&gcc PCIE_1_A_CLK>,
1094 <&gcc PCIE_1_H_CLK>,
1095 <&gcc PCIE_1_PHY_CLK>,
1096 <&gcc PCIE_1_AUX_CLK>,
1097 <&gcc PCIE_1_ALT_REF_CLK>;
1098 clock-names = "core", "iface", "phy", "aux", "ref";
1099
1100 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1101 assigned-clock-rates = <100000000>;
1102
1103 resets = <&gcc PCIE_1_ACLK_RESET>,
1104 <&gcc PCIE_1_HCLK_RESET>,
1105 <&gcc PCIE_1_POR_RESET>,
1106 <&gcc PCIE_1_PCI_RESET>,
1107 <&gcc PCIE_1_PHY_RESET>,
1108 <&gcc PCIE_1_EXT_RESET>;
1109 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1110
1111 pinctrl-0 = <&pcie1_pins>;
1112 pinctrl-names = "default";
1113
1114 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1115
1116 phy-tx0-term-offset = <7>;
1117
1118 status = "disabled";
1119 };
1120
1121 pcie2: pci@1b900000 {
1122 compatible = "qcom,pcie-ipq8064";
1123 reg = <0x1b900000 0x1000
1124 0x1b902000 0x80
1125 0x1ba00000 0x100
1126 0x35f00000 0x100000>;
1127 reg-names = "dbi", "elbi", "parf", "config";
1128 device_type = "pci";
1129 linux,pci-domain = <2>;
1130 bus-range = <0x00 0xff>;
1131 num-lanes = <1>;
1132 #address-cells = <3>;
1133 #size-cells = <2>;
1134
1135 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1136 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1137
1138 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1139 interrupt-names = "msi";
1140 #interrupt-cells = <1>;
1141 interrupt-map-mask = <0 0 0 0x7>;
1142 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1143 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1144 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1145 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1146
1147 clocks = <&gcc PCIE_2_A_CLK>,
1148 <&gcc PCIE_2_H_CLK>,
1149 <&gcc PCIE_2_PHY_CLK>,
1150 <&gcc PCIE_2_AUX_CLK>,
1151 <&gcc PCIE_2_ALT_REF_CLK>;
1152 clock-names = "core", "iface", "phy", "aux", "ref";
1153
1154 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1155 assigned-clock-rates = <100000000>;
1156
1157 resets = <&gcc PCIE_2_ACLK_RESET>,
1158 <&gcc PCIE_2_HCLK_RESET>,
1159 <&gcc PCIE_2_POR_RESET>,
1160 <&gcc PCIE_2_PCI_RESET>,
1161 <&gcc PCIE_2_PHY_RESET>,
1162 <&gcc PCIE_2_EXT_RESET>;
1163 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1164
1165 pinctrl-0 = <&pcie2_pins>;
1166 pinctrl-names = "default";
1167
1168 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1169
1170 phy-tx0-term-offset = <7>;
1171
1172 status = "disabled";
1173 };
1174
1175 adm_dma: dma@18300000 {
1176 compatible = "qcom,adm";
1177 reg = <0x18300000 0x100000>;
1178 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1179 #dma-cells = <1>;
1180
1181 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1182 clock-names = "core", "iface";
1183
1184 resets = <&gcc ADM0_RESET>,
1185 <&gcc ADM0_PBUS_RESET>,
1186 <&gcc ADM0_C0_RESET>,
1187 <&gcc ADM0_C1_RESET>,
1188 <&gcc ADM0_C2_RESET>;
1189 reset-names = "clk", "pbus", "c0", "c1", "c2";
1190 qcom,ee = <0>;
1191
1192 status = "disabled";
1193 };
1194
1195 nand@1ac00000 {
1196 compatible = "qcom,ipq806x-nand";
1197 reg = <0x1ac00000 0x800>;
1198
1199 clocks = <&gcc EBI2_CLK>,
1200 <&gcc EBI2_AON_CLK>;
1201 clock-names = "core", "aon";
1202
1203 dmas = <&adm_dma 3>;
1204 dma-names = "rxtx";
1205 qcom,cmd-crci = <15>;
1206 qcom,data-crci = <3>;
1207
1208 status = "disabled";
1209
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1212 };
1213
1214 nss_common: syscon@03000000 {
1215 compatible = "syscon";
1216 reg = <0x03000000 0x0000FFFF>;
1217 };
1218
1219 qsgmii_csr: syscon@1bb00000 {
1220 compatible = "syscon";
1221 reg = <0x1bb00000 0x000001FF>;
1222 };
1223
1224 stmmac_axi_setup: stmmac-axi-config {
1225 snps,wr_osr_lmt = <7>;
1226 snps,rd_osr_lmt = <7>;
1227 snps,blen = <16 0 0 0 0 0 0>;
1228 };
1229
1230 gmac0: ethernet@37000000 {
1231 device_type = "network";
1232 compatible = "qcom,ipq806x-gmac";
1233 reg = <0x37000000 0x200000>;
1234 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1235 interrupt-names = "macirq";
1236
1237 snps,axi-config = <&stmmac_axi_setup>;
1238 snps,pbl = <32>;
1239 snps,aal = <1>;
1240
1241 qcom,nss-common = <&nss_common>;
1242 qcom,qsgmii-csr = <&qsgmii_csr>;
1243
1244 clocks = <&gcc GMAC_CORE1_CLK>;
1245 clock-names = "stmmaceth";
1246
1247 resets = <&gcc GMAC_CORE1_RESET>;
1248 reset-names = "stmmaceth";
1249
1250 status = "disabled";
1251 };
1252
1253 gmac1: ethernet@37200000 {
1254 device_type = "network";
1255 compatible = "qcom,ipq806x-gmac";
1256 reg = <0x37200000 0x200000>;
1257 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1258 interrupt-names = "macirq";
1259
1260 snps,axi-config = <&stmmac_axi_setup>;
1261 snps,pbl = <32>;
1262 snps,aal = <1>;
1263
1264 qcom,nss-common = <&nss_common>;
1265 qcom,qsgmii-csr = <&qsgmii_csr>;
1266
1267 clocks = <&gcc GMAC_CORE2_CLK>;
1268 clock-names = "stmmaceth";
1269
1270 resets = <&gcc GMAC_CORE2_RESET>;
1271 reset-names = "stmmaceth";
1272
1273 status = "disabled";
1274 };
1275
1276 gmac2: ethernet@37400000 {
1277 device_type = "network";
1278 compatible = "qcom,ipq806x-gmac";
1279 reg = <0x37400000 0x200000>;
1280 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1281 interrupt-names = "macirq";
1282
1283 snps,axi-config = <&stmmac_axi_setup>;
1284 snps,pbl = <32>;
1285 snps,aal = <1>;
1286
1287 qcom,nss-common = <&nss_common>;
1288 qcom,qsgmii-csr = <&qsgmii_csr>;
1289
1290 clocks = <&gcc GMAC_CORE3_CLK>;
1291 clock-names = "stmmaceth";
1292
1293 resets = <&gcc GMAC_CORE3_RESET>;
1294 reset-names = "stmmaceth";
1295
1296 status = "disabled";
1297 };
1298
1299 gmac3: ethernet@37600000 {
1300 device_type = "network";
1301 compatible = "qcom,ipq806x-gmac";
1302 reg = <0x37600000 0x200000>;
1303 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1304 interrupt-names = "macirq";
1305
1306 snps,axi-config = <&stmmac_axi_setup>;
1307 snps,pbl = <32>;
1308 snps,aal = <1>;
1309
1310 qcom,nss-common = <&nss_common>;
1311 qcom,qsgmii-csr = <&qsgmii_csr>;
1312
1313 clocks = <&gcc GMAC_CORE4_CLK>;
1314 clock-names = "stmmaceth";
1315
1316 resets = <&gcc GMAC_CORE4_RESET>;
1317 reset-names = "stmmaceth";
1318
1319 status = "disabled";
1320 };
1321
1322 /* Temporary fixed regulator */
1323 vsdcc_fixed: vsdcc-regulator {
1324 compatible = "regulator-fixed";
1325 regulator-name = "SDCC Power";
1326 regulator-min-microvolt = <3300000>;
1327 regulator-max-microvolt = <3300000>;
1328 regulator-always-on;
1329 };
1330
1331 sdcc1bam:dma@12402000 {
1332 compatible = "qcom,bam-v1.3.0";
1333 reg = <0x12402000 0x8000>;
1334 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&gcc SDC1_H_CLK>;
1336 clock-names = "bam_clk";
1337 #dma-cells = <1>;
1338 qcom,ee = <0>;
1339 };
1340
1341 sdcc3bam:dma@12182000 {
1342 compatible = "qcom,bam-v1.3.0";
1343 reg = <0x12182000 0x8000>;
1344 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&gcc SDC3_H_CLK>;
1346 clock-names = "bam_clk";
1347 #dma-cells = <1>;
1348 qcom,ee = <0>;
1349 };
1350
1351 amba {
1352 compatible = "arm,amba-bus";
1353 #address-cells = <1>;
1354 #size-cells = <1>;
1355 ranges;
1356 sdcc1: sdcc@12400000 {
1357 status = "disabled";
1358 compatible = "arm,pl18x", "arm,primecell";
1359 arm,primecell-periphid = <0x00051180>;
1360 reg = <0x12400000 0x2000>;
1361 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1362 interrupt-names = "cmd_irq";
1363 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1364 clock-names = "mclk", "apb_pclk";
1365 bus-width = <8>;
1366 max-frequency = <96000000>;
1367 non-removable;
1368 cap-sd-highspeed;
1369 cap-mmc-highspeed;
1370 vmmc-supply = <&vsdcc_fixed>;
1371 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1372 dma-names = "tx", "rx";
1373 };
1374
1375 sdcc3: sdcc@12180000 {
1376 compatible = "arm,pl18x", "arm,primecell";
1377 arm,primecell-periphid = <0x00051180>;
1378 status = "disabled";
1379 reg = <0x12180000 0x2000>;
1380 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1381 interrupt-names = "cmd_irq";
1382 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1383 clock-names = "mclk", "apb_pclk";
1384 bus-width = <8>;
1385 cap-sd-highspeed;
1386 cap-mmc-highspeed;
1387 max-frequency = <192000000>;
1388 #mmc-ddr-1_8v;
1389 sd-uhs-sdr104;
1390 sd-uhs-ddr50;
1391 vqmmc-supply = <&vsdcc_fixed>;
1392 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1393 dma-names = "tx", "rx";
1394 };
1395 };
1396 };
1397
1398 sfpb_mutex: sfpb-mutex {
1399 compatible = "qcom,sfpb-mutex";
1400 syscon = <&sfpb_mutex_block 4 4>;
1401
1402 #hwlock-cells = <1>;
1403 };
1404
1405 smem {
1406 compatible = "qcom,smem";
1407 memory-region = <&smem>;
1408 hwlocks = <&sfpb_mutex 3>;
1409 };
1410 };
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