3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
27 next-level-cache = <&L2>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 voltage-tolerance = <5>;
35 cooling-min-state = <0>;
36 cooling-max-state = <10>;
38 cpu-idle-states = <&CPU_SPC>;
42 compatible = "qcom,krait";
43 enable-method = "qcom,kpss-acc-v1";
46 next-level-cache = <&L2>;
49 clocks = <&kraitcc 1>, <&kraitcc 4>;
50 clock-names = "cpu", "l2";
51 clock-latency = <100000>;
52 cpu-supply = <&smb208_s2b>;
53 cooling-min-state = <0>;
54 cooling-max-state = <10>;
56 cpu-idle-states = <&CPU_SPC>;
66 qcom,l2-rates = <384000000 1000000000 1200000000>;
71 compatible = "qcom,idle-state-spc",
73 entry-latency-us = <400>;
74 exit-latency-us = <900>;
75 min-residency-us = <3000>;
82 polling-delay-passive = <250>;
83 polling-delay = <1000>;
85 thermal-sensors = <&gcc 5>;
86 coefficients = <1132 0>;
90 temperature = <75000>;
95 temperature = <110000>;
103 polling-delay-passive = <250>;
104 polling-delay = <1000>;
106 thermal-sensors = <&gcc 6>;
107 coefficients = <1132 0>;
111 temperature = <75000>;
116 temperature = <110000>;
124 polling-delay-passive = <250>;
125 polling-delay = <1000>;
127 thermal-sensors = <&gcc 7>;
128 coefficients = <1199 0>;
132 temperature = <75000>;
137 temperature = <110000>;
145 polling-delay-passive = <250>;
146 polling-delay = <1000>;
148 thermal-sensors = <&gcc 8>;
149 coefficients = <1132 0>;
153 temperature = <75000>;
158 temperature = <110000>;
167 compatible = "qcom,krait-pmu";
168 interrupts = <1 10 0x304>;
172 #address-cells = <1>;
177 reg = <0x40000000 0x1000000>;
181 smem: smem@41000000 {
182 reg = <0x41000000 0x200000>;
189 compatible = "fixed-clock";
191 clock-frequency = <25000000>;
195 compatible = "fixed-clock";
197 clock-frequency = <25000000>;
200 sleep_clk: sleep_clk {
201 compatible = "fixed-clock";
202 clock-frequency = <32768>;
209 compatible = "qcom,scm-apq8064";
211 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
212 clock-names = "core";
216 kraitcc: clock-controller {
217 compatible = "qcom,krait-cc-v1";
223 qcom,speed0-pvs0-bin-v0 =
224 < 1400000000 1250000 >,
225 < 1200000000 1200000 >,
226 < 1000000000 1150000 >,
227 < 800000000 1100000 >,
228 < 600000000 1050000 >,
229 < 384000000 1000000 >;
231 qcom,speed0-pvs1-bin-v0 =
232 < 1400000000 1175000 >,
233 < 1200000000 1125000 >,
234 < 1000000000 1075000 >,
235 < 800000000 1025000 >,
236 < 600000000 975000 >,
237 < 384000000 925000 >;
239 qcom,speed0-pvs2-bin-v0 =
240 < 1400000000 1125000 >,
241 < 1200000000 1075000 >,
242 < 1000000000 1025000 >,
243 < 800000000 995000 >,
244 < 600000000 925000 >,
245 < 384000000 875000 >;
247 qcom,speed0-pvs3-bin-v0 =
248 < 1400000000 1050000 >,
249 < 1200000000 1000000 >,
250 < 1000000000 950000 >,
251 < 800000000 900000 >,
252 < 600000000 850000 >,
253 < 384000000 800000 >;
257 #address-cells = <1>;
260 compatible = "simple-bus";
263 compatible = "qcom,lpass-cpu";
265 clocks = <&lcc AHBIX_CLK>,
268 clock-names = "ahbix-clk",
271 interrupts = <0 85 1>;
272 interrupt-names = "lpass-irq-lpaif";
273 reg = <0x28100000 0x10000>;
274 reg-names = "lpass-lpaif";
277 qfprom: qfprom@700000 {
278 compatible = "qcom,qfprom", "syscon";
279 reg = <0x00700000 0x1000>;
280 #address-cells = <1>;
287 tsens_backup: backup_calib {
293 compatible = "qcom,rpm-ipq8064";
294 reg = <0x108000 0x1000>;
295 qcom,ipc = <&l2cc 0x8 2>;
297 interrupts = <0 19 0>,
300 interrupt-names = "ack",
304 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
307 #address-cells = <1>;
310 rpmcc: clock-controller {
311 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
316 compatible = "qcom,rpm-smb208-regulators";
319 regulator-min-microvolt = <1050000>;
320 regulator-max-microvolt = <1150000>;
322 qcom,switch-mode-frequency = <1200000>;
327 regulator-min-microvolt = <1050000>;
328 regulator-max-microvolt = <1150000>;
330 qcom,switch-mode-frequency = <1200000>;
334 regulator-min-microvolt = < 800000>;
335 regulator-max-microvolt = <1250000>;
337 qcom,switch-mode-frequency = <1200000>;
341 regulator-min-microvolt = < 800000>;
342 regulator-max-microvolt = <1250000>;
344 qcom,switch-mode-frequency = <1200000>;
350 compatible = "qcom,prng";
351 reg = <0x1a500000 0x200>;
352 clocks = <&gcc PRNG_CLK>;
353 clock-names = "core";
356 qcom_pinmux: pinmux@800000 {
357 compatible = "qcom,ipq8064-pinctrl";
358 reg = <0x800000 0x4000>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 interrupts = <0 16 0x4>;
366 pcie0_pins: pcie0_pinmux {
369 function = "pcie1_rst";
370 drive-strength = <2>;
375 pcie1_pins: pcie1_pinmux {
378 function = "pcie2_rst";
379 drive-strength = <2>;
384 pcie2_pins: pcie2_pinmux {
387 function = "pcie3_rst";
388 drive-strength = <2>;
395 intc: interrupt-controller@2000000 {
396 compatible = "qcom,msm-qgic2";
397 interrupt-controller;
398 #interrupt-cells = <3>;
399 reg = <0x02000000 0x1000>,
404 compatible = "qcom,kpss-timer", "qcom,msm-timer";
405 interrupts = <1 1 0x301>,
410 reg = <0x0200a000 0x100>;
411 clock-frequency = <25000000>,
413 clocks = <&sleep_clk>;
414 clock-names = "sleep";
415 cpu-offset = <0x80000>;
418 acc0: clock-controller@2088000 {
419 compatible = "qcom,kpss-acc-v1";
420 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
421 clock-output-names = "acpu0_aux";
424 acc1: clock-controller@2098000 {
425 compatible = "qcom,kpss-acc-v1";
426 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
427 clock-output-names = "acpu1_aux";
430 l2cc: clock-controller@2011000 {
431 compatible = "qcom,kpss-gcc", "syscon";
432 reg = <0x2011000 0x1000>;
433 clock-output-names = "acpu_l2_aux";
436 saw0: regulator@2089000 {
437 compatible = "qcom,saw2", "syscon";
438 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
442 saw1: regulator@2099000 {
443 compatible = "qcom,saw2", "syscon";
444 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
448 saw_l2: regulator@02012000 {
449 compatible = "qcom,saw2", "syscon";
450 reg = <0x02012000 0x1000>;
454 sic_non_secure: sic-non-secure@12100000 {
455 compatible = "syscon";
456 reg = <0x12100000 0x10000>;
459 gsbi2: gsbi@12480000 {
460 compatible = "qcom,gsbi-v1.0.0";
462 reg = <0x12480000 0x100>;
463 clocks = <&gcc GSBI2_H_CLK>;
464 clock-names = "iface";
465 #address-cells = <1>;
470 syscon-tcsr = <&tcsr>;
472 uart2: serial@12490000 {
473 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
474 reg = <0x12490000 0x1000>,
476 interrupts = <0 195 0x0>;
477 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
478 clock-names = "core", "iface";
483 compatible = "qcom,i2c-qup-v1.1.1";
484 reg = <0x124a0000 0x1000>;
485 interrupts = <0 196 0>;
487 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
488 clock-names = "core", "iface";
491 #address-cells = <1>;
497 gsbi4: gsbi@16300000 {
498 compatible = "qcom,gsbi-v1.0.0";
500 reg = <0x16300000 0x100>;
501 clocks = <&gcc GSBI4_H_CLK>;
502 clock-names = "iface";
503 #address-cells = <1>;
508 syscon-tcsr = <&tcsr>;
510 gsbi4_serial: serial@16340000 {
511 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
512 reg = <0x16340000 0x1000>,
514 interrupts = <0 152 0x0>;
515 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
516 clock-names = "core", "iface";
521 compatible = "qcom,i2c-qup-v1.1.1";
522 reg = <0x16380000 0x1000>;
523 interrupts = <0 153 0>;
525 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
526 clock-names = "core", "iface";
529 #address-cells = <1>;
534 gsbi5: gsbi@1a200000 {
535 compatible = "qcom,gsbi-v1.0.0";
537 reg = <0x1a200000 0x100>;
538 clocks = <&gcc GSBI5_H_CLK>;
539 clock-names = "iface";
540 #address-cells = <1>;
545 syscon-tcsr = <&tcsr>;
547 uart5: serial@1a240000 {
548 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
549 reg = <0x1a240000 0x1000>,
551 interrupts = <0 154 0x0>;
552 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
553 clock-names = "core", "iface";
558 compatible = "qcom,i2c-qup-v1.1.1";
559 reg = <0x1a280000 0x1000>;
560 interrupts = <0 155 0>;
562 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
563 clock-names = "core", "iface";
566 #address-cells = <1>;
571 compatible = "qcom,spi-qup-v1.1.1";
572 reg = <0x1a280000 0x1000>;
573 interrupts = <0 155 0>;
575 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
576 clock-names = "core", "iface";
579 #address-cells = <1>;
584 sata_phy: sata-phy@1b400000 {
585 compatible = "qcom,ipq806x-sata-phy";
586 reg = <0x1b400000 0x200>;
588 clocks = <&gcc SATA_PHY_CFG_CLK>;
596 compatible = "qcom,ipq806x-ahci", "generic-ahci";
597 reg = <0x29000000 0x180>;
599 interrupts = <0 209 0x0>;
601 clocks = <&gcc SFAB_SATA_S_H_CLK>,
604 <&gcc SATA_RXOOB_CLK>,
605 <&gcc SATA_PMALIVE_CLK>;
606 clock-names = "slave_face", "iface", "core",
609 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
610 assigned-clock-rates = <100000000>, <100000000>;
613 phy-names = "sata-phy";
618 compatible = "qcom,ssbi";
619 reg = <0x00500000 0x1000>;
620 qcom,controller-type = "pmic-arbiter";
623 gcc: clock-controller@900000 {
624 compatible = "qcom,gcc-ipq8064";
625 reg = <0x00900000 0x4000>;
626 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
627 nvmem-cell-names = "calib", "calib_backup";
630 #power-domain-cells = <1>;
631 #thermal-sensor-cells = <1>;
634 tcsr: syscon@1a400000 {
635 compatible = "qcom,tcsr-ipq8064", "syscon";
636 reg = <0x1a400000 0x100>;
639 lcc: clock-controller@28000000 {
640 compatible = "qcom,lcc-ipq8064";
641 reg = <0x28000000 0x1000>;
646 sfpb_mutex_block: syscon@1200600 {
647 compatible = "syscon";
648 reg = <0x01200600 0x100>;
651 hs_phy_1: phy@100f8800 {
652 compatible = "qcom,dwc3-hs-usb-phy";
653 reg = <0x100f8800 0x30>;
654 clocks = <&gcc USB30_1_UTMI_CLK>;
661 ss_phy_1: phy@100f8830 {
662 compatible = "qcom,dwc3-ss-usb-phy";
663 reg = <0x100f8830 0x30>;
664 clocks = <&gcc USB30_1_MASTER_CLK>;
671 hs_phy_0: phy@110f8800 {
672 compatible = "qcom,dwc3-hs-usb-phy";
673 reg = <0x110f8800 0x30>;
674 clocks = <&gcc USB30_0_UTMI_CLK>;
681 ss_phy_0: phy@110f8830 {
682 compatible = "qcom,dwc3-ss-usb-phy";
683 reg = <0x110f8830 0x30>;
684 clocks = <&gcc USB30_0_MASTER_CLK>;
692 compatible = "qcom,dwc3";
693 #address-cells = <1>;
695 clocks = <&gcc USB30_0_MASTER_CLK>;
696 clock-names = "core";
698 syscon-tcsr = <&tcsr 0xb0 1>;
705 compatible = "snps,dwc3";
706 reg = <0x11000000 0xcd00>;
707 interrupts = <0 110 0x4>;
708 phys = <&hs_phy_0>, <&ss_phy_0>;
709 phy-names = "usb2-phy", "usb3-phy";
711 snps,dis_u3_susphy_quirk;
716 compatible = "qcom,dwc3";
717 #address-cells = <1>;
719 clocks = <&gcc USB30_1_MASTER_CLK>;
720 clock-names = "core";
722 syscon-tcsr = <&tcsr 0xb0 0>;
729 compatible = "snps,dwc3";
730 reg = <0x10000000 0xcd00>;
731 interrupts = <0 205 0x4>;
732 phys = <&hs_phy_1>, <&ss_phy_1>;
733 phy-names = "usb2-phy", "usb3-phy";
735 snps,dis_u3_susphy_quirk;
739 pcie0: pci@1b500000 {
740 compatible = "qcom,pcie-ipq8064";
741 reg = <0x1b500000 0x1000
744 0x0ff00000 0x100000>;
745 reg-names = "dbi", "elbi", "parf", "config";
747 linux,pci-domain = <0>;
748 bus-range = <0x00 0xff>;
750 #address-cells = <3>;
753 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
754 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
756 interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
757 interrupt-names = "msi";
758 #interrupt-cells = <1>;
759 interrupt-map-mask = <0 0 0 0x7>;
760 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
761 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
762 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
763 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
765 clocks = <&gcc PCIE_A_CLK>,
769 <&gcc PCIE_ALT_REF_CLK>;
770 clock-names = "core", "iface", "phy", "aux", "ref";
772 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
773 assigned-clock-rates = <100000000>;
775 resets = <&gcc PCIE_ACLK_RESET>,
776 <&gcc PCIE_HCLK_RESET>,
777 <&gcc PCIE_POR_RESET>,
778 <&gcc PCIE_PCI_RESET>,
779 <&gcc PCIE_PHY_RESET>,
780 <&gcc PCIE_EXT_RESET>;
781 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
783 pinctrl-0 = <&pcie0_pins>;
784 pinctrl-names = "default";
786 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
791 pcie1: pci@1b700000 {
792 compatible = "qcom,pcie-ipq8064";
793 reg = <0x1b700000 0x1000
796 0x31f00000 0x100000>;
797 reg-names = "dbi", "elbi", "parf", "config";
799 linux,pci-domain = <1>;
800 bus-range = <0x00 0xff>;
802 #address-cells = <3>;
805 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
806 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
808 interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
809 interrupt-names = "msi";
810 #interrupt-cells = <1>;
811 interrupt-map-mask = <0 0 0 0x7>;
812 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
813 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
814 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
815 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
817 clocks = <&gcc PCIE_1_A_CLK>,
819 <&gcc PCIE_1_PHY_CLK>,
820 <&gcc PCIE_1_AUX_CLK>,
821 <&gcc PCIE_1_ALT_REF_CLK>;
822 clock-names = "core", "iface", "phy", "aux", "ref";
824 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
825 assigned-clock-rates = <100000000>;
827 resets = <&gcc PCIE_1_ACLK_RESET>,
828 <&gcc PCIE_1_HCLK_RESET>,
829 <&gcc PCIE_1_POR_RESET>,
830 <&gcc PCIE_1_PCI_RESET>,
831 <&gcc PCIE_1_PHY_RESET>,
832 <&gcc PCIE_1_EXT_RESET>;
833 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
835 pinctrl-0 = <&pcie1_pins>;
836 pinctrl-names = "default";
838 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
843 pcie2: pci@1b900000 {
844 compatible = "qcom,pcie-ipq8064";
845 reg = <0x1b900000 0x1000
848 0x35f00000 0x100000>;
849 reg-names = "dbi", "elbi", "parf", "config";
851 linux,pci-domain = <2>;
852 bus-range = <0x00 0xff>;
854 #address-cells = <3>;
857 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
858 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
860 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
861 interrupt-names = "msi";
862 #interrupt-cells = <1>;
863 interrupt-map-mask = <0 0 0 0x7>;
864 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
865 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
866 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
867 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
869 clocks = <&gcc PCIE_2_A_CLK>,
871 <&gcc PCIE_2_PHY_CLK>,
872 <&gcc PCIE_2_AUX_CLK>,
873 <&gcc PCIE_2_ALT_REF_CLK>;
874 clock-names = "core", "iface", "phy", "aux", "ref";
876 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
877 assigned-clock-rates = <100000000>;
879 resets = <&gcc PCIE_2_ACLK_RESET>,
880 <&gcc PCIE_2_HCLK_RESET>,
881 <&gcc PCIE_2_POR_RESET>,
882 <&gcc PCIE_2_PCI_RESET>,
883 <&gcc PCIE_2_PHY_RESET>,
884 <&gcc PCIE_2_EXT_RESET>;
885 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
887 pinctrl-0 = <&pcie2_pins>;
888 pinctrl-names = "default";
890 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
895 adm_dma: dma@18300000 {
896 compatible = "qcom,adm";
897 reg = <0x18300000 0x100000>;
898 interrupts = <0 170 0>;
901 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
902 clock-names = "core", "iface";
904 resets = <&gcc ADM0_RESET>,
905 <&gcc ADM0_PBUS_RESET>,
906 <&gcc ADM0_C0_RESET>,
907 <&gcc ADM0_C1_RESET>,
908 <&gcc ADM0_C2_RESET>;
909 reset-names = "clk", "pbus", "c0", "c1", "c2";
916 compatible = "qcom,ipq806x-nand";
917 reg = <0x1ac00000 0x800>;
919 clocks = <&gcc EBI2_CLK>,
921 clock-names = "core", "aon";
925 qcom,cmd-crci = <15>;
926 qcom,data-crci = <3>;
930 #address-cells = <1>;
934 nss_common: syscon@03000000 {
935 compatible = "syscon";
936 reg = <0x03000000 0x0000FFFF>;
939 qsgmii_csr: syscon@1bb00000 {
940 compatible = "syscon";
941 reg = <0x1bb00000 0x000001FF>;
944 stmmac_axi_setup: stmmac-axi-config {
945 snps,wr_osr_lmt = <7>;
946 snps,rd_osr_lmt = <7>;
947 snps,blen = <16 0 0 0 0 0 0>;
950 gmac0: ethernet@37000000 {
951 device_type = "network";
952 compatible = "qcom,ipq806x-gmac";
953 reg = <0x37000000 0x200000>;
954 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
955 interrupt-names = "macirq";
957 snps,axi-config = <&stmmac_axi_setup>;
961 qcom,nss-common = <&nss_common>;
962 qcom,qsgmii-csr = <&qsgmii_csr>;
964 clocks = <&gcc GMAC_CORE1_CLK>;
965 clock-names = "stmmaceth";
967 resets = <&gcc GMAC_CORE1_RESET>;
968 reset-names = "stmmaceth";
973 gmac1: ethernet@37200000 {
974 device_type = "network";
975 compatible = "qcom,ipq806x-gmac";
976 reg = <0x37200000 0x200000>;
977 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
978 interrupt-names = "macirq";
980 snps,axi-config = <&stmmac_axi_setup>;
984 qcom,nss-common = <&nss_common>;
985 qcom,qsgmii-csr = <&qsgmii_csr>;
987 clocks = <&gcc GMAC_CORE2_CLK>;
988 clock-names = "stmmaceth";
990 resets = <&gcc GMAC_CORE2_RESET>;
991 reset-names = "stmmaceth";
996 gmac2: ethernet@37400000 {
997 device_type = "network";
998 compatible = "qcom,ipq806x-gmac";
999 reg = <0x37400000 0x200000>;
1000 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1001 interrupt-names = "macirq";
1003 snps,axi-config = <&stmmac_axi_setup>;
1007 qcom,nss-common = <&nss_common>;
1008 qcom,qsgmii-csr = <&qsgmii_csr>;
1010 clocks = <&gcc GMAC_CORE3_CLK>;
1011 clock-names = "stmmaceth";
1013 resets = <&gcc GMAC_CORE3_RESET>;
1014 reset-names = "stmmaceth";
1016 status = "disabled";
1019 gmac3: ethernet@37600000 {
1020 device_type = "network";
1021 compatible = "qcom,ipq806x-gmac";
1022 reg = <0x37600000 0x200000>;
1023 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1024 interrupt-names = "macirq";
1026 snps,axi-config = <&stmmac_axi_setup>;
1030 qcom,nss-common = <&nss_common>;
1031 qcom,qsgmii-csr = <&qsgmii_csr>;
1033 clocks = <&gcc GMAC_CORE4_CLK>;
1034 clock-names = "stmmaceth";
1036 resets = <&gcc GMAC_CORE4_RESET>;
1037 reset-names = "stmmaceth";
1039 status = "disabled";
1043 sfpb_mutex: sfpb-mutex {
1044 compatible = "qcom,sfpb-mutex";
1045 syscon = <&sfpb_mutex_block 4 4>;
1047 #hwlock-cells = <1>;
1051 compatible = "qcom,smem";
1052 memory-region = <&smem>;
1053 hwlocks = <&sfpb_mutex 3>;