1 #include "qcom-ipq8064-v1.0.dtsi"
4 model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
5 compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
8 reg = <0x42000000 0x1e000000>;
9 device_type = "memory";
17 reg = <0x41200000 0x300000>;
23 serial0 = &gsbi4_serial;
28 stdout-path = "serial0:115200n8";
33 i2c4_pins: i2c4_pinmux {
34 pins = "gpio12", "gpio13";
39 nand_pins: nand_pins {
41 pins = "gpio34", "gpio35", "gpio36",
44 drive-strength = <10>;
51 drive-strength = <10>;
56 pins = "gpio40", "gpio41", "gpio42",
57 "gpio43", "gpio44", "gpio45",
60 drive-strength = <10>;
65 mdio0_pins: mdio0_pins {
67 pins = "gpio0", "gpio1";
74 rgmii2_pins: rgmii2_pins {
76 pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
77 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
90 qcom,mode = <GSBI_PROT_I2C_UART>;
98 * The i2c device on gsbi4 should not be enabled.
99 * On ipq806x designs gsbi4 i2c is meant for exclusive
100 * RPM usage. Turning this on in kernel manifests as
101 * i2c failure for the RPM.
106 qcom,mode = <GSBI_PROT_SPI>;
111 spi-max-frequency = <50000000>;
113 pinctrl-0 = <&spi_pins>;
114 pinctrl-names = "default";
116 cs-gpios = <&qcom_pinmux 20 0>;
119 compatible = "s25fl256s1";
120 #address-cells = <1>;
122 spi-max-frequency = <50000000>;
126 compatible = "qcom,smem";
152 pinctrl-0 = <&nand_pins>;
153 pinctrl-names = "default";
157 compatible = "qcom,nandcs";
159 nand-ecc-strength = <4>;
160 nand-bus-width = <8>;
161 nand-ecc-step-size = <512>;
164 compatible = "qcom,smem";
172 pinctrl-0 = <&mdio0_pins>;
173 pinctrl-names = "default";
175 phy0: ethernet-phy@0 {
177 qca,ar8327-initvals = <
178 0x00004 0x7600000 /* PAD0_MODE */
179 0x00008 0x1000000 /* PAD5_MODE */
180 0x0000c 0x80 /* PAD6_MODE */
181 0x000e4 0x6a545 /* MAC_POWER_SEL */
182 0x000e0 0xc74164de /* SGMII_CTRL */
183 0x0007c 0x4e /* PORT0_STATUS */
184 0x00094 0x4e /* PORT6_STATUS */
188 phy4: ethernet-phy@4 {
198 pinctrl-0 = <&rgmii2_pins>;
199 pinctrl-names = "default";