1 #include "qcom-ipq8064-v1.0.dtsi"
4 model = "Qualcomm IPQ8064/AP161";
5 compatible = "qcom,ipq8064-ap161", "qcom,ipq8064";
8 reg = <0x42000000 0x1e000000>;
9 device_type = "memory";
17 reg = <0x41200000 0x300000>;
23 serial0 = &gsbi4_serial;
28 stdout-path = "serial0:115200n8";
32 mdio0: mdio@37000000 {
36 compatible = "qcom,ipq8064-mdio", "syscon";
37 reg = <0x37000000 0x200000>;
38 resets = <&gcc GMAC_CORE1_RESET>;
39 reset-names = "stmmaceth";
40 clocks = <&gcc GMAC_CORE1_CLK>;
41 clock-names = "stmmaceth";
43 pinctrl-0 = <&mdio0_pins>;
44 pinctrl-names = "default";
46 phy0: ethernet-phy@0 {
48 qca,ar8327-initvals = <
49 0x00004 0x7600000 /* PAD0_MODE */
50 0x00008 0x1000000 /* PAD5_MODE */
51 0x0000c 0x20080 /* PAD6_MODE */
52 0x000e4 0x6a545 /* MAC_POWER_SEL */
53 0x000e0 0xc74164de /* SGMII_CTRL */
54 0x0007c 0x4e /* PORT0_STATUS */
55 0x00094 0x4e /* PORT6_STATUS */
59 phy4: ethernet-phy@4 {
66 phy3: ethernet-phy@3 {
67 device_type = "ethernet-phy";
75 i2c4_pins: i2c4_pinmux {
76 pins = "gpio12", "gpio13";
83 pins = "gpio18", "gpio19", "gpio21";
85 drive-strength = <10>;
89 nand_pins: nand_pins {
91 pins = "gpio34", "gpio35", "gpio36",
94 drive-strength = <10>;
101 drive-strength = <10>;
106 pins = "gpio40", "gpio41", "gpio42",
107 "gpio43", "gpio44", "gpio45",
110 drive-strength = <10>;
115 mdio0_pins: mdio0_pins {
117 pins = "gpio0", "gpio1";
119 drive-strength = <8>;
124 rgmii2_pins: rgmii2_pins {
126 pins = "gpio2", "gpio27", "gpio28",
127 "gpio29", "gpio30", "gpio31",
128 "gpio32", "gpio51", "gpio52",
129 "gpio59", "gpio60", "gpio61",
132 drive-strength = <8>;
139 qcom,mode = <GSBI_PROT_I2C_UART>;
146 * The i2c device on gsbi4 should not be enabled.
147 * On ipq806x designs gsbi4 i2c is meant for exclusive
148 * RPM usage. Turning this on in kernel manifests as
149 * i2c failure for the RPM.
154 qcom,mode = <GSBI_PROT_SPI>;
159 spi-max-frequency = <50000000>;
161 pinctrl-0 = <&spi_pins>;
162 pinctrl-names = "default";
164 cs-gpios = <&qcom_pinmux 20 0>;
167 compatible = "s25fl256s1";
168 #address-cells = <1>;
170 spi-max-frequency = <50000000>;
174 compatible = "qcom,smem";
212 pinctrl-0 = <&nand_pins>;
213 pinctrl-names = "default";
217 compatible = "qcom,nandcs";
219 nand-ecc-strength = <4>;
220 nand-bus-width = <8>;
221 nand-ecc-step-size = <512>;
224 compatible = "qcom,smem";
234 pinctrl-0 = <&rgmii2_pins>;
235 pinctrl-names = "default";