07201adf6d14d9567433dcfbbbefa9d2a58d01e4
[openwrt/staging/stintel.git] / target / linux / ipq806x / files-5.4 / arch / arm / boot / dts / qcom-ipq8064-wpq864.dts
1 /*
2 * BSD LICENSE
3 *
4 * Copyright (C) 2017 Christian Mehlis <christian@m3hlis.de>
5 * Copyright (C) 2018 Mathias Kresin <dev@kresin.me>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the names of the copyright holders nor the names of any
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include "qcom-ipq8064-v1.0.dtsi"
35
36 #include <dt-bindings/input/input.h>
37 #include <dt-bindings/soc/qcom,tcsr.h>
38
39 / {
40 compatible = "compex,wpq864", "qcom,ipq8064";
41 model = "Compex WPQ864";
42
43 aliases {
44 mdio-gpio0 = &mdio0;
45 serial0 = &gsbi4_serial;
46 ethernet0 = &gmac1;
47 ethernet1 = &gmac0;
48
49 led-boot = &led_pass;
50 led-failsafe = &led_fail;
51 led-running = &led_pass;
52 led-upgrade = &led_pass;
53 };
54
55 leds {
56 compatible = "gpio-leds";
57
58 pinctrl-0 = <&led_pins>;
59 pinctrl-names = "default";
60
61 rss4 {
62 label = "wpq864:green:rss4";
63 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
64 };
65
66 rss3 {
67 label = "wpq864:green:rss3";
68 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
69 default-state = "keep";
70 };
71
72 rss2 {
73 label = "wpq864:orange:rss2";
74 gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
75 };
76
77 rss1 {
78 label = "wpq864:red:rss1";
79 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
80 };
81
82 led_pass: pass {
83 label = "wpq864:green:pass";
84 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
85 };
86
87 led_fail: fail {
88 label = "wpq864:green:fail";
89 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
90 };
91
92 usb {
93 label = "wpq864:green:usb";
94 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
95 };
96
97 usb-pcie {
98 label = "wpq864:green:usb-pcie";
99 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
100 };
101 };
102
103 keys {
104 compatible = "gpio-keys";
105
106 pinctrl-0 = <&button_pins>;
107 pinctrl-names = "default";
108
109 reset {
110 label = "reset";
111 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
112 linux,code = <KEY_RESTART>;
113 };
114 };
115
116 beeper {
117 compatible = "gpio-beeper";
118
119 pinctrl-0 = <&beeper_pins>;
120 pinctrl-names = "default";
121
122 gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
123 };
124 };
125
126 &rpm {
127 pinctrl-0 = <&rpm_pins>;
128 pinctrl-names = "default";
129 };
130
131 &nand_controller {
132 status = "okay";
133
134 pinctrl-0 = <&nand_pins>;
135 pinctrl-names = "default";
136
137 mt29f2g08abbeah4@0 {
138 compatible = "qcom,nandcs";
139
140 reg = <0>;
141
142 nand-ecc-strength = <4>;
143 nand-bus-width = <8>;
144 nand-ecc-step-size = <512>;
145
146 partitions {
147 compatible = "fixed-partitions";
148 #address-cells = <1>;
149 #size-cells = <1>;
150
151 SBL1@0 {
152 label = "SBL1";
153 reg = <0x0000000 0x0040000>;
154 read-only;
155 };
156
157 MIBIB@40000 {
158 label = "MIBIB";
159 reg = <0x0040000 0x0140000>;
160 read-only;
161 };
162
163 SBL2@180000 {
164 label = "SBL2";
165 reg = <0x0180000 0x0140000>;
166 read-only;
167 };
168
169 SBL3@2c0000 {
170 label = "SBL3";
171 reg = <0x02c0000 0x0280000>;
172 read-only;
173 };
174
175 DDRCONFIG@540000 {
176 label = "DDRCONFIG";
177 reg = <0x0540000 0x0120000>;
178 read-only;
179 };
180
181 SSD@660000 {
182 label = "SSD";
183 reg = <0x0660000 0x0120000>;
184 read-only;
185 };
186
187 TZ@780000 {
188 label = "TZ";
189 reg = <0x0780000 0x0280000>;
190 read-only;
191 };
192
193 RPM@a00000 {
194 label = "RPM";
195 reg = <0x0a00000 0x0280000>;
196 read-only;
197 };
198
199 APPSBL@c80000 {
200 label = "APPSBL";
201 reg = <0x0c80000 0x0500000>;
202 read-only;
203 };
204
205 APPSBLENV@1180000 {
206 label = "APPSBLENV";
207 reg = <0x1180000 0x0080000>;
208 };
209
210 ART@1200000 {
211 label = "ART";
212 reg = <0x1200000 0x0140000>;
213 };
214
215 ubi@1340000 {
216 label = "ubi";
217 reg = <0x1340000 0x4000000>;
218 };
219
220 BOOTCONFIG@5340000 {
221 label = "BOOTCONFIG";
222 reg = <0x5340000 0x0060000>;
223 };
224
225 SBL2-1@53a0000- {
226 label = "SBL2_1";
227 reg = <0x53a0000 0x0140000>;
228 read-only;
229 };
230
231 SBL3-1@54e0000 {
232 label = "SBL3_1";
233 reg = <0x54e0000 0x0280000>;
234 read-only;
235 };
236
237 DDRCONFIG-1@5760000 {
238 label = "DDRCONFIG_1";
239 reg = <0x5760000 0x0120000>;
240 read-only;
241 };
242
243 SSD-1@5880000 {
244 label = "SSD_1";
245 reg = <0x5880000 0x0120000>;
246 read-only;
247 };
248
249 TZ-1@59a0000 {
250 label = "TZ_1";
251 reg = <0x59a0000 0x0280000>;
252 read-only;
253 };
254
255 RPM-1@5c20000 {
256 label = "RPM_1";
257 reg = <0x5c20000 0x0280000>;
258 read-only;
259 };
260
261 BOOTCONFIG1@5ea0000 {
262 label = "BOOTCONFIG1";
263 reg = <0x5ea0000 0x0060000>;
264 };
265
266 APPSBL-1@5f00000 {
267 label = "APPSBL_1";
268 reg = <0x5f00000 0x0500000>;
269 read-only;
270 };
271
272 ubi-1@6400000 {
273 label = "ubi_1";
274 reg = <0x6400000 0x4000000>;
275 };
276
277 unused@a400000 {
278 label = "unused";
279 reg = <0xa400000 0x5c00000>;
280 };
281 };
282 };
283 };
284
285 &adm_dma {
286 status = "okay";
287 };
288
289 &mdio0 {
290 status = "okay";
291
292 pinctrl-0 = <&mdio0_pins>;
293 pinctrl-names = "default";
294
295 ethernet-phy@0 {
296 reg = <0>;
297 qca,ar8327-initvals = <
298 0x00004 0x7600000 /* PAD0_MODE */
299 0x00008 0x1000000 /* PAD5_MODE */
300 0x0000c 0x80 /* PAD6_MODE */
301 0x000e4 0x6a545 /* MAC_POWER_SEL */
302 0x000e0 0xc74164de /* SGMII_CTRL */
303 0x0007c 0x4e /* PORT0_STATUS */
304 0x00094 0x4e /* PORT6_STATUS */
305 >;
306 };
307
308 ethernet-phy@4 {
309 reg = <4>;
310 };
311 };
312
313 &gmac1 {
314 status = "okay";
315
316 pinctrl-0 = <&rgmii2_pins>;
317 pinctrl-names = "default";
318
319 phy-mode = "rgmii";
320 qcom,id = <1>;
321
322 fixed-link {
323 speed = <1000>;
324 full-duplex;
325 };
326 };
327
328 &gmac2 {
329 status = "okay";
330
331 phy-mode = "sgmii";
332 qcom,id = <2>;
333
334 fixed-link {
335 speed = <1000>;
336 full-duplex;
337 };
338 };
339
340 &gsbi4 {
341 status = "okay";
342 qcom,mode = <GSBI_PROT_I2C_UART>;
343 };
344
345 &gsbi4_serial {
346 status = "okay";
347
348 pinctrl-0 = <&uart0_pins>;
349 pinctrl-names = "default";
350 };
351
352 &gsbi5 {
353 status = "okay";
354
355 qcom,mode = <GSBI_PROT_SPI>;
356
357 spi@1a280000 {
358 status = "okay";
359
360 pinctrl-0 = <&spi_pins>;
361 pinctrl-names = "default";
362
363 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
364
365 s25fl256s1@0 {
366 compatible = "jedec,spi-nor";
367 #address-cells = <1>;
368 #size-cells = <1>;
369 reg = <0>;
370 spi-max-frequency = <50000000>;
371 };
372 };
373 };
374
375 &ss_phy_0 { /* USB3 port 0 SS phy */
376 status = "okay";
377
378 rx_eq = <2>;
379 tx_deamp_3_5db = <32>;
380 mpll = <160>;
381 };
382
383 &ss_phy_1 { /* USB3 port 1 SS phy */
384 status = "okay";
385
386 rx_eq = <2>;
387 tx_deamp_3_5db = <32>;
388 mpll = <160>;
389 };
390
391 &pcie0 {
392 status = "okay";
393
394 /delete-property/ pinctrl-0;
395 /delete-property/ pinctrl-names;
396 /delete-property/ perst-gpios;
397 };
398
399 &pcie1 {
400 status = "okay";
401 };
402
403 &pcie2 {
404 status = "okay";
405
406 /delete-property/ pinctrl-0;
407 /delete-property/ pinctrl-names;
408 /delete-property/ perst-gpios;
409 };
410
411 &qcom_pinmux {
412 pinctrl-names = "default";
413 pinctrl-0 = <&state_default>;
414
415 state_default: pinctrl0 {
416 pcie0_pcie2_perst {
417 pins = "gpio3";
418 function = "gpio";
419 drive-strength = <2>;
420 bias-disable;
421 output-high;
422 };
423 };
424
425 led_pins: led_pins {
426 mux {
427 pins = "gpio7", "gpio8", "gpio9", "gpio22",
428 "gpio23", "gpio24", "gpio25", "gpio53";
429 function = "gpio";
430 drive-strength = <2>;
431 bias-pull-up;
432 };
433 };
434
435 button_pins: button_pins {
436 mux {
437 pins = "gpio54";
438 function = "gpio";
439 drive-strength = <2>;
440 bias-pull-up;
441 };
442 };
443
444 beeper_pins: beeper_pins {
445 mux {
446 pins = "gpio55";
447 function = "gpio";
448 drive-strength = <2>;
449 bias-pull-up;
450 };
451 };
452
453 rpm_pins: rpm_pins {
454 mux {
455 pins = "gpio12", "gpio13";
456 function = "gsbi4";
457 drive-strength = <10>;
458 bias-disable;
459 };
460 };
461
462 uart0_pins: uart0_pins {
463 mux {
464 pins = "gpio10", "gpio11";
465 function = "gsbi4";
466 drive-strength = <10>;
467 bias-disable;
468 };
469 };
470
471 spi_pins: spi_pins {
472 mux {
473 pins = "gpio18", "gpio19";
474 function = "gsbi5";
475 drive-strength = <10>;
476 bias-pull-down;
477 };
478
479 clk {
480 pins = "gpio21";
481 function = "gsbi5";
482 drive-strength = <12>;
483 bias-pull-down;
484 };
485
486 cs {
487 pins = "gpio20";
488 function = "gpio";
489 drive-strength = <10>;
490 bias-pull-up;
491 };
492 };
493 };
494
495 &usb3_0 {
496 status = "okay";
497 };
498
499 &usb3_1 {
500 status = "okay";
501 };
502
503 &tcsr {
504 qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
505 };