1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq8064-v2.0-smb208.dtsi"
5 #include <dt-bindings/input/input.h>
9 bootargs = "console=ttyMSM0,115200n8";
10 /* append to bootargs adding the root deviceblock nbr from bootloader */
11 append-rootblock = "ubi.mtd=";
16 /* eax500 routers reuse the pcie2 reset pin for switch reset pin */
17 switch_reset: switch_reset_pins {
21 drive-strength = <12>;
66 compatible = "qcom,nandcs";
68 nand-ecc-strength = <4>;
70 nand-ecc-step-size = <512>;
73 qcom,boot-partitions = <0x0 0x0c80000>;
75 partitions: partitions {
76 compatible = "fixed-partitions";
82 reg = <0x0000000 0x0040000>;
88 reg = <0x0040000 0x0140000>;
94 reg = <0x0180000 0x0140000>;
100 reg = <0x02c0000 0x0280000>;
106 reg = <0x0540000 0x0120000>;
112 reg = <0x0660000 0x0120000>;
118 reg = <0x0780000 0x0280000>;
124 reg = <0x0a00000 0x0280000>;
128 art: partition@c80000 {
130 reg = <0x0c80000 0x0140000>;
136 reg = <0x0dc0000 0x0100000>;
142 reg = <0x0ec0000 0x0040000>;
147 reg = <0x0f00000 0x0040000>;
152 reg = <0x0f40000 0x0040000>;
157 reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
162 reg = <0x1380000 0x2400000>;
167 reg = <0x3780000 0x2800000>;
172 reg = <0x3b80000 0x2400000>;
181 pinctrl-0 = <&mdio0_pins>;
182 pinctrl-names = "default";
184 /* Switch from documentation require at least 10ms for reset */
185 reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
186 reset-post-delay-us = <12000>;
188 phy0: ethernet-phy@0 {
190 qca,ar8327-initvals = <
191 0x00004 0x7600000 /* PAD0_MODE */
192 0x00008 0x1000000 /* PAD5_MODE */
193 0x0000c 0x80 /* PAD6_MODE */
194 0x00010 0x2613a0 /* PWS_REG */
195 0x000e4 0x6a545 /* MAC_POWER_SEL */
196 0x000e0 0xc74164de /* SGMII_CTRL */
197 0x0007c 0x4e /* PORT0_STATUS */
198 0x00094 0x4e /* PORT6_STATUS */
209 pinctrl-0 = <&rgmii2_pins>;
210 pinctrl-names = "default";