1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "qcom-ipq8064-v2.0-smb208.dtsi"
5 #include <dt-bindings/input/input.h>
9 bootargs = "console=ttyMSM0,115200n8";
10 /* append to bootargs adding the root deviceblock nbr from bootloader */
11 append-rootblock = "ubi.mtd=";
16 /* eax500 routers reuse the pcie2 reset pin for switch reset pin */
17 switch_reset: switch_reset_pins {
21 drive-strength = <12>;
66 compatible = "qcom,nandcs";
68 nand-ecc-strength = <4>;
70 nand-ecc-step-size = <512>;
73 qcom,boot-partitions = <0x0 0x0c80000>;
75 partitions: partitions {
76 compatible = "fixed-partitions";
82 reg = <0x0000000 0x0040000>;
88 reg = <0x0040000 0x0140000>;
94 reg = <0x0180000 0x0140000>;
100 reg = <0x02c0000 0x0280000>;
106 reg = <0x0540000 0x0120000>;
112 reg = <0x0660000 0x0120000>;
118 reg = <0x0780000 0x0280000>;
124 reg = <0x0a00000 0x0280000>;
128 art: partition@c80000 {
130 reg = <0x0c80000 0x0140000>;
136 reg = <0x0dc0000 0x0100000>;
142 reg = <0x0ec0000 0x0040000>;
147 reg = <0x0f00000 0x0040000>;
152 reg = <0x0f40000 0x0040000>;
157 reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
162 reg = <0x1380000 0x2400000>;
167 reg = <0x3780000 0x2800000>;
172 reg = <0x3b80000 0x2400000>;
181 pinctrl-0 = <&mdio0_pins>;
182 pinctrl-names = "default";
184 /* Switch from documentation require at least 10ms for reset */
185 reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
186 reset-post-delay-us = <12000>;
189 compatible = "qca,qca8337";
190 #address-cells = <1>;
195 #address-cells = <1>;
203 tx-internal-delay-ps = <1000>;
204 rx-internal-delay-ps = <1000>;
215 phy-mode = "internal";
216 phy-handle = <&phy_port1>;
222 phy-mode = "internal";
223 phy-handle = <&phy_port2>;
229 phy-mode = "internal";
230 phy-handle = <&phy_port3>;
236 phy-mode = "internal";
237 phy-handle = <&phy_port4>;
243 phy-mode = "internal";
244 phy-handle = <&phy_port5>;
252 qca,sgmii-enable-pll;
262 #address-cells = <1>;
294 pinctrl-0 = <&rgmii2_pins>;
295 pinctrl-names = "default";