1 // SPDX-License-Identifier: GPL-2.0-or-later
3 #include "qcom-ipq8065-smb208.dtsi"
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
8 model = "Arris TR4400 v2";
9 compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
12 reg = <0x42000000 0x1e000000>;
13 device_type = "memory";
17 led-boot = &led_status_blue;
18 led-failsafe = &led_status_red;
19 led-running = &led_status_blue;
20 led-upgrade = &led_status_red;
24 bootargs = "rootfstype=squashfs noinitrd";
28 compatible = "gpio-keys";
29 pinctrl-0 = <&button_pins>;
30 pinctrl-names = "default";
34 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_RESTART>;
36 debounce-interval = <60>;
42 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
43 linux,code = <KEY_WPS_BUTTON>;
44 debounce-interval = <60>;
50 compatible = "gpio-leds";
51 pinctrl-0 = <&led_pins>;
52 pinctrl-names = "default";
54 led_status_red: status_red {
55 function = LED_FUNCTION_STATUS;
56 color = <LED_COLOR_ID_RED>;
57 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
60 led_status_blue: status_blue {
61 function = LED_FUNCTION_STATUS;
62 color = <LED_COLOR_ID_BLUE>;
63 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
69 button_pins: button_pins {
71 pins = "gpio6", "gpio54";
80 pins = "gpio7", "gpio8";
87 rgmii2_pins: rgmii2-pins {
89 pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
97 drive-strength = <12>;
103 qcom,mode = <GSBI_PROT_SPI>;
109 pinctrl-0 = <&spi_pins>;
110 pinctrl-names = "default";
112 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
115 compatible = "everspin,mr25h256";
116 spi-max-frequency = <40000000>;
127 compatible = "qcom,nandcs";
129 nand-ecc-strength = <4>;
130 nand-bus-width = <8>;
131 nand-ecc-step-size = <512>;
133 qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
136 compatible = "fixed-partitions";
137 #address-cells = <1>;
142 reg = <0x0000000 0x0040000>;
147 reg = <0x0040000 0x0140000>;
152 reg = <0x0180000 0x0140000>;
157 reg = <0x02c0000 0x0280000>;
161 label = "0:DDRCONFIG";
162 reg = <0x0540000 0x0120000>;
167 reg = <0x0660000 0x0120000>;
172 reg = <0x0780000 0x0280000>;
177 reg = <0x0a00000 0x0280000>;
182 reg = <0x0c80000 0x0500000>;
186 label = "0:APPSBLENV";
187 reg = <0x1180000 0x0080000>;
191 reg = <0x1200000 0x0140000>;
195 compatible = "fixed-layout";
196 #address-cells = <1>;
199 precal_ART_1000: precal@1000 {
200 reg = <0x1000 0x2f20>;
202 precal_ART_5000: precal@5000 {
203 reg = <0x5000 0x2f20>;
207 stock_partition@1340000 {
208 label = "stock_rootfs";
209 reg = <0x1340000 0x4000000>;
211 compatible = "fixed-partitions";
212 #address-cells = <1>;
217 reg = <0x0 0x4000000>;
221 label = "0:BOOTCONFIG";
222 reg = <0x5340000 0x0060000>;
227 reg = <0x53a0000 0x0140000>;
232 reg = <0x54e0000 0x0280000>;
236 label = "0:DDRCONFIG_1";
237 reg = <0x5760000 0x0120000>;
242 reg = <0x5880000 0x0120000>;
247 reg = <0x59a0000 0x0280000>;
252 reg = <0x5c20000 0x0280000>;
256 label = "0:BOOTCONFIG1";
257 reg = <0x5ea0000 0x0060000>;
261 label = "0:APPSBL_1";
262 reg = <0x5f00000 0x0500000>;
265 stock_partition@6400000 {
266 label = "stock_rootfs_1";
267 reg = <0x6400000 0x4000000>;
269 compatible = "fixed-partitions";
270 #address-cells = <1>;
275 reg = <0x0 0x100000>;
278 compatible = "fixed-layout";
279 #address-cells = <1>;
282 macaddr_fw_env_0: macaddr@0 {
285 macaddr_fw_env_6: macaddr@6 {
288 macaddr_fw_env_c: macaddr@c {
291 macaddr_fw_env_12: macaddr@12 {
294 macaddr_fw_env_18: macaddr@18 {
302 reg = <0x100000 0x9b00000>;
305 stock_partition@a400000 {
306 label = "stock_fw_env";
307 reg = <0xa400000 0x0100000>;
309 stock_partition@a500000 {
310 label = "stock_config";
311 reg = <0xa500000 0x0800000>;
313 stock_partition@ad00000 {
315 reg = <0xad00000 0x0200000>;
317 stock_partition@af00000 {
318 label = "stock_scfgmgr";
319 reg = <0xaf00000 0x0100000>;
328 pinctrl-0 = <&mdio0_pins>;
329 pinctrl-names = "default";
332 compatible = "qca,qca8337";
333 #address-cells = <1>;
338 #address-cells = <1>;
346 tx-internal-delay-ps = <1000>;
347 rx-internal-delay-ps = <1000>;
358 phy-mode = "internal";
359 phy-handle = <&phy_port1>;
365 phy-mode = "internal";
366 phy-handle = <&phy_port2>;
372 phy-mode = "internal";
373 phy-handle = <&phy_port3>;
379 phy-mode = "internal";
380 phy-handle = <&phy_port4>;
388 qca,sgmii-enable-pll;
398 #address-cells = <1>;
419 phy7: ethernet-phy@7 {
429 nvmem-cells = <&macaddr_fw_env_18>;
430 nvmem-cell-names = "mac-address";
432 pinctrl-0 = <&rgmii2_pins>;
433 pinctrl-names = "default";
446 nvmem-cells = <&macaddr_fw_env_0>;
447 nvmem-cell-names = "mac-address";
459 phy-handle = <&phy7>;
461 nvmem-cells = <&macaddr_fw_env_6>;
462 nvmem-cell-names = "mac-address";
483 reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
484 pinctrl-0 = <&pcie0_pins>;
485 pinctrl-names = "default";
488 reg = <0x00000000 0 0 0 0>;
489 #address-cells = <3>;
494 compatible = "pci168c,0046";
495 reg = <0x00010000 0 0 0 0>;
497 nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
498 nvmem-cell-names = "pre-calibration", "mac-address";
505 reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
506 pinctrl-0 = <&pcie1_pins>;
507 pinctrl-names = "default";
508 max-link-speed = <1>;
511 reg = <0x00000000 0 0 0 0>;
512 #address-cells = <3>;
517 compatible = "pci168c,0040";
518 reg = <0x00010000 0 0 0 0>;
520 nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
521 nvmem-cell-names = "pre-calibration", "mac-address";