1 From eb07c23d45ddf10fa89296e6c6c6aed553d8bbf5 Mon Sep 17 00:00:00 2001
2 From: Rohit Vaswani <rvaswani@codeaurora.org>
3 Date: Fri, 21 Jun 2013 17:09:13 -0700
4 Subject: [PATCH 014/182] ARM: qcom: Add SMP support for KPSSv2
6 Implement support for the Krait CPU release sequence when the
7 CPUs are part of the second version of the Krait processor
10 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
14 arch/arm/mach-qcom/platsmp.c | 123 ++++++++++++++++++++++++++++++++++++++++++
15 1 file changed, 123 insertions(+)
17 --- a/arch/arm/mach-qcom/platsmp.c
18 +++ b/arch/arm/mach-qcom/platsmp.c
20 #define L2DT_SLP BIT(3)
23 +#define APC_PWR_GATE_CTL 0x14
24 +#define BHS_CNT_SHIFT 24
25 +#define LDO_PWR_DWN_SHIFT 16
26 +#define LDO_BYP_SHIFT 8
27 +#define BHS_SEG_SHIFT 1
28 +#define BHS_EN BIT(0)
30 #define APCS_SAW2_VCTL 0x14
31 +#define APCS_SAW2_2_VCTL 0x1c
33 extern void secondary_startup(void);
35 @@ -160,6 +168,106 @@ out_acc:
39 +static int kpssv2_release_secondary(unsigned int cpu)
42 + struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
43 + void __iomem *l2_saw_base;
47 + cpu_node = of_get_cpu_node(cpu, NULL);
51 + acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
57 + l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
63 + saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
69 + reg = of_iomap(acc_node, 0);
75 + l2_saw_base = of_iomap(saw_node, 0);
81 + /* Turn on the BHS, turn off LDO Bypass and power down LDO */
82 + reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
83 + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
85 + /* wait for the BHS to settle */
88 + /* Turn on BHS segments */
89 + reg_val |= 0x3f << BHS_SEG_SHIFT;
90 + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
92 + /* wait for the BHS to settle */
95 + /* Finally turn on the bypass so that BHS supplies power */
96 + reg_val |= 0x3f << LDO_BYP_SHIFT;
97 + writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
99 + /* enable max phases */
100 + writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
104 + reg_val = COREPOR_RST | CLAMP;
105 + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
110 + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
114 + reg_val &= ~COREPOR_RST;
115 + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
118 + reg_val |= CORE_PWRD_UP;
119 + writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
124 + iounmap(l2_saw_base);
128 + of_node_put(saw_node);
130 + of_node_put(l2_node);
132 + of_node_put(acc_node);
134 + of_node_put(cpu_node);
139 static DEFINE_PER_CPU(int, cold_boot_done);
141 static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
142 @@ -204,6 +312,11 @@ static int kpssv1_boot_secondary(unsigne
143 return qcom_boot_secondary(cpu, kpssv1_release_secondary);
146 +static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
148 + return qcom_boot_secondary(cpu, kpssv2_release_secondary);
151 static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
154 @@ -253,3 +366,13 @@ static struct smp_operations qcom_smp_kp
157 CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
159 +static struct smp_operations qcom_smp_kpssv2_ops __initdata = {
160 + .smp_prepare_cpus = qcom_smp_prepare_cpus,
161 + .smp_secondary_init = qcom_secondary_init,
162 + .smp_boot_secondary = kpssv2_boot_secondary,
163 +#ifdef CONFIG_HOTPLUG_CPU
164 + .cpu_die = qcom_cpu_die,
167 +CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);