1 From 5a8f026acb4a7a6c6d0c868cc1790363640b9b8f Mon Sep 17 00:00:00 2001
2 From: Georgi Djakov <gdjakov@mm-sol.com>
3 Date: Mon, 10 Mar 2014 17:37:12 +0200
4 Subject: [PATCH 047/182] mmc: sdhci-msm: Initial support for Qualcomm
7 This platform driver adds the initial support of Secure Digital Host
8 Controller Interface compliant controller found in Qualcomm chipsets.
10 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
11 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
12 Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com>
13 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
14 Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
15 Signed-off-by: Chris Ball <chris@printf.net>
17 drivers/mmc/host/Kconfig | 13 +++
18 drivers/mmc/host/Makefile | 1 +
19 drivers/mmc/host/sdhci-msm.c | 208 ++++++++++++++++++++++++++++++++++++++++++
20 3 files changed, 222 insertions(+)
21 create mode 100644 drivers/mmc/host/sdhci-msm.c
23 --- a/drivers/mmc/host/Kconfig
24 +++ b/drivers/mmc/host/Kconfig
25 @@ -334,6 +334,19 @@ config MMC_ATMELMCI
30 + tristate "Qualcomm SDHCI Controller Support"
31 + depends on ARCH_QCOM
32 + depends on MMC_SDHCI_PLTFM
34 + This selects the Secure Digital Host Controller Interface (SDHCI)
35 + support present in Qualcomm SOCs. The controller supports
36 + SD/MMC/SDIO devices.
38 + If you have a controller with this interface, say Y or M here.
43 tristate "Qualcomm SDCC Controller Support"
44 depends on MMC && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50)
45 --- a/drivers/mmc/host/Makefile
46 +++ b/drivers/mmc/host/Makefile
47 @@ -65,6 +65,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhc
48 obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
49 obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
50 obj-$(CONFIG_MMC_SDHCI_BCM2835) += sdhci-bcm2835.o
51 +obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
53 ifeq ($(CONFIG_CB710_DEBUG),y)
54 CFLAGS-cb710-mmc += -DDEBUG
56 +++ b/drivers/mmc/host/sdhci-msm.c
59 + * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
61 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
63 + * This program is free software; you can redistribute it and/or modify
64 + * it under the terms of the GNU General Public License version 2 and
65 + * only version 2 as published by the Free Software Foundation.
67 + * This program is distributed in the hope that it will be useful,
68 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
69 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
70 + * GNU General Public License for more details.
74 +#include <linux/module.h>
75 +#include <linux/of_device.h>
76 +#include <linux/regulator/consumer.h>
77 +#include <linux/delay.h>
79 +#include "sdhci-pltfm.h"
81 +#define CORE_HC_MODE 0x78
82 +#define HC_MODE_EN 0x1
83 +#define CORE_POWER 0x0
84 +#define CORE_SW_RST BIT(7)
87 +struct sdhci_msm_host {
88 + struct platform_device *pdev;
89 + void __iomem *core_mem; /* MSM SDCC mapped address */
90 + struct clk *clk; /* main SD/MMC bus clock */
91 + struct clk *pclk; /* SDHC peripheral bus clock */
92 + struct clk *bus_clk; /* SDHC bus voter clock */
93 + struct mmc_host *mmc;
94 + struct sdhci_pltfm_data sdhci_msm_pdata;
97 +/* Platform specific tuning */
98 +static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
101 + * Tuning is required for SDR104, HS200 and HS400 cards and if the clock
102 + * frequency greater than 100MHz in those modes. The standard tuning
103 + * procedure should not be executed, but a custom implementation will be
104 + * added here instead.
109 +static const struct of_device_id sdhci_msm_dt_match[] = {
110 + { .compatible = "qcom,sdhci-msm-v4" },
114 +MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
116 +static struct sdhci_ops sdhci_msm_ops = {
117 + .platform_execute_tuning = sdhci_msm_execute_tuning,
120 +static int sdhci_msm_probe(struct platform_device *pdev)
122 + struct sdhci_host *host;
123 + struct sdhci_pltfm_host *pltfm_host;
124 + struct sdhci_msm_host *msm_host;
125 + struct resource *core_memres;
129 + msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
133 + msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops;
134 + host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0);
136 + return PTR_ERR(host);
138 + pltfm_host = sdhci_priv(host);
139 + pltfm_host->priv = msm_host;
140 + msm_host->mmc = host->mmc;
141 + msm_host->pdev = pdev;
143 + ret = mmc_of_parse(host->mmc);
147 + sdhci_get_of_property(pdev);
149 + /* Setup SDCC bus voter clock. */
150 + msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
151 + if (!IS_ERR(msm_host->bus_clk)) {
152 + /* Vote for max. clk rate for max. performance */
153 + ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
156 + ret = clk_prepare_enable(msm_host->bus_clk);
161 + /* Setup main peripheral bus clock */
162 + msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
163 + if (IS_ERR(msm_host->pclk)) {
164 + ret = PTR_ERR(msm_host->pclk);
165 + dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
166 + goto bus_clk_disable;
169 + ret = clk_prepare_enable(msm_host->pclk);
171 + goto bus_clk_disable;
173 + /* Setup SDC MMC clock */
174 + msm_host->clk = devm_clk_get(&pdev->dev, "core");
175 + if (IS_ERR(msm_host->clk)) {
176 + ret = PTR_ERR(msm_host->clk);
177 + dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
181 + ret = clk_prepare_enable(msm_host->clk);
185 + core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
186 + msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
188 + if (IS_ERR(msm_host->core_mem)) {
189 + dev_err(&pdev->dev, "Failed to remap registers\n");
190 + ret = PTR_ERR(msm_host->core_mem);
194 + /* Reset the core and Enable SDHC mode */
195 + writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
196 + CORE_SW_RST, msm_host->core_mem + CORE_POWER);
198 + /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
199 + usleep_range(1000, 5000);
200 + if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
201 + dev_err(&pdev->dev, "Stuck in reset\n");
206 + /* Set HC_MODE_EN bit in HC_MODE register */
207 + writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
209 + host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
210 + host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE;
212 + host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
213 + dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
214 + host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
215 + SDHCI_VENDOR_VER_SHIFT));
217 + ret = sdhci_add_host(host);
224 + clk_disable_unprepare(msm_host->clk);
226 + clk_disable_unprepare(msm_host->pclk);
228 + if (!IS_ERR(msm_host->bus_clk))
229 + clk_disable_unprepare(msm_host->bus_clk);
231 + sdhci_pltfm_free(pdev);
235 +static int sdhci_msm_remove(struct platform_device *pdev)
237 + struct sdhci_host *host = platform_get_drvdata(pdev);
238 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
239 + struct sdhci_msm_host *msm_host = pltfm_host->priv;
240 + int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
243 + sdhci_remove_host(host, dead);
244 + sdhci_pltfm_free(pdev);
245 + clk_disable_unprepare(msm_host->clk);
246 + clk_disable_unprepare(msm_host->pclk);
247 + if (!IS_ERR(msm_host->bus_clk))
248 + clk_disable_unprepare(msm_host->bus_clk);
252 +static struct platform_driver sdhci_msm_driver = {
253 + .probe = sdhci_msm_probe,
254 + .remove = sdhci_msm_remove,
256 + .name = "sdhci_msm",
257 + .owner = THIS_MODULE,
258 + .of_match_table = sdhci_msm_dt_match,
262 +module_platform_driver(sdhci_msm_driver);
264 +MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
265 +MODULE_LICENSE("GPL v2");