1 From b5bc51d44485c7ce0ca180a8c5de11a206f686e8 Mon Sep 17 00:00:00 2001
2 From: Josh Cartwright <joshc@codeaurora.org>
3 Date: Wed, 12 Feb 2014 13:44:25 -0600
4 Subject: [PATCH 057/182] spmi: pmic_arb: add support for interrupt handling
6 The Qualcomm PMIC Arbiter, in addition to being a basic SPMI controller,
7 also implements interrupt handling for slave devices. Note, this is
8 outside the scope of SPMI, as SPMI leaves interrupt handling completely
11 Extend the driver to provide a irq_chip implementation and chained irq
12 handling which allows for these interrupts to be used.
14 Cc: Thomas Gleixner <tglx@linutronix.de>
15 Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
16 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
18 drivers/spmi/Kconfig | 1 +
19 drivers/spmi/spmi-pmic-arb.c | 377 +++++++++++++++++++++++++++++++++++++++++-
20 2 files changed, 376 insertions(+), 2 deletions(-)
22 diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
23 index 80b7901..075bd79 100644
24 --- a/drivers/spmi/Kconfig
25 +++ b/drivers/spmi/Kconfig
26 @@ -13,6 +13,7 @@ if SPMI
27 config SPMI_MSM_PMIC_ARB
28 tristate "Qualcomm MSM SPMI Controller (PMIC Arbiter)"
30 + depends on IRQ_DOMAIN
31 depends on ARCH_MSM || COMPILE_TEST
34 diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
35 index 2dd27e8..246e03a 100644
36 --- a/drivers/spmi/spmi-pmic-arb.c
37 +++ b/drivers/spmi/spmi-pmic-arb.c
39 #include <linux/err.h>
40 #include <linux/interrupt.h>
42 +#include <linux/irqchip/chained_irq.h>
43 +#include <linux/irqdomain.h>
44 +#include <linux/irq.h>
45 #include <linux/kernel.h>
46 #include <linux/module.h>
48 @@ -103,6 +106,14 @@ enum pmic_arb_cmd_op_code {
49 * @cnfg: address of the PMIC Arbiter configuration registers.
50 * @lock: lock to synchronize accesses.
51 * @channel: which channel to use for accesses.
52 + * @irq: PMIC ARB interrupt.
53 + * @ee: the current Execution Environment
54 + * @min_apid: minimum APID (used for bounding IRQ search)
55 + * @max_apid: maximum APID
56 + * @mapping_table: in-memory copy of PPID -> APID mapping table.
57 + * @domain: irq domain object for PMIC IRQ domain
58 + * @spmic: SPMI controller object
59 + * @apid_to_ppid: cached mapping from APID to PPID
61 struct spmi_pmic_arb_dev {
63 @@ -110,6 +121,14 @@ struct spmi_pmic_arb_dev {
71 + u32 mapping_table[SPMI_MAPPING_TABLE_LEN];
72 + struct irq_domain *domain;
73 + struct spmi_controller *spmic;
74 + u16 apid_to_ppid[256];
77 static inline u32 pmic_arb_base_read(struct spmi_pmic_arb_dev *dev, u32 offset)
78 @@ -306,12 +325,316 @@ static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
83 + QPNPINT_REG_RT_STS = 0x10,
84 + QPNPINT_REG_SET_TYPE = 0x11,
85 + QPNPINT_REG_POLARITY_HIGH = 0x12,
86 + QPNPINT_REG_POLARITY_LOW = 0x13,
87 + QPNPINT_REG_LATCHED_CLR = 0x14,
88 + QPNPINT_REG_EN_SET = 0x15,
89 + QPNPINT_REG_EN_CLR = 0x16,
90 + QPNPINT_REG_LATCHED_STS = 0x18,
93 +struct spmi_pmic_arb_qpnpint_type {
94 + u8 type; /* 1 -> edge */
99 +/* Simplified accessor functions for irqchip callbacks */
100 +static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
103 + struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
104 + u8 sid = d->hwirq >> 24;
105 + u8 per = d->hwirq >> 16;
107 + if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
108 + (per << 8) + reg, buf, len))
109 + dev_err_ratelimited(&pa->spmic->dev,
110 + "failed irqchip transaction on %x\n",
114 +static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
116 + struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
117 + u8 sid = d->hwirq >> 24;
118 + u8 per = d->hwirq >> 16;
120 + if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid,
121 + (per << 8) + reg, buf, len))
122 + dev_err_ratelimited(&pa->spmic->dev,
123 + "failed irqchip transaction on %x\n",
127 +static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid)
133 + status = readl_relaxed(pa->intr + SPMI_PIC_IRQ_STATUS(apid));
135 + id = ffs(status) - 1;
136 + status &= ~(1 << id);
137 + irq = irq_find_mapping(pa->domain,
138 + pa->apid_to_ppid[apid] << 16
141 + generic_handle_irq(irq);
145 +static void pmic_arb_chained_irq(unsigned int irq, struct irq_desc *desc)
147 + struct spmi_pmic_arb_dev *pa = irq_get_handler_data(irq);
148 + struct irq_chip *chip = irq_get_chip(irq);
149 + void __iomem *intr = pa->intr;
150 + int first = pa->min_apid >> 5;
151 + int last = pa->max_apid >> 5;
155 + chained_irq_enter(chip, desc);
157 + for (i = first; i <= last; ++i) {
158 + status = readl_relaxed(intr +
159 + SPMI_PIC_OWNER_ACC_STATUS(pa->ee, i));
161 + id = ffs(status) - 1;
162 + status &= ~(1 << id);
163 + periph_interrupt(pa, id + i * 32);
167 + chained_irq_exit(chip, desc);
170 +static void qpnpint_irq_ack(struct irq_data *d)
172 + struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
173 + u8 irq = d->hwirq >> 8;
174 + u8 apid = d->hwirq;
175 + unsigned long flags;
178 + raw_spin_lock_irqsave(&pa->lock, flags);
179 + writel_relaxed(1 << irq, pa->intr + SPMI_PIC_IRQ_CLEAR(apid));
180 + raw_spin_unlock_irqrestore(&pa->lock, flags);
183 + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
186 +static void qpnpint_irq_mask(struct irq_data *d)
188 + struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
189 + u8 irq = d->hwirq >> 8;
190 + u8 apid = d->hwirq;
191 + unsigned long flags;
195 + raw_spin_lock_irqsave(&pa->lock, flags);
196 + status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
197 + if (status & SPMI_PIC_ACC_ENABLE_BIT) {
198 + status = status & ~SPMI_PIC_ACC_ENABLE_BIT;
199 + writel_relaxed(status, pa->intr + SPMI_PIC_ACC_ENABLE(apid));
201 + raw_spin_unlock_irqrestore(&pa->lock, flags);
204 + qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
207 +static void qpnpint_irq_unmask(struct irq_data *d)
209 + struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
210 + u8 irq = d->hwirq >> 8;
211 + u8 apid = d->hwirq;
212 + unsigned long flags;
216 + raw_spin_lock_irqsave(&pa->lock, flags);
217 + status = readl_relaxed(pa->intr + SPMI_PIC_ACC_ENABLE(apid));
218 + if (!(status & SPMI_PIC_ACC_ENABLE_BIT)) {
219 + writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT,
220 + pa->intr + SPMI_PIC_ACC_ENABLE(apid));
222 + raw_spin_unlock_irqrestore(&pa->lock, flags);
225 + qpnpint_spmi_write(d, QPNPINT_REG_EN_SET, &data, 1);
228 +static void qpnpint_irq_enable(struct irq_data *d)
230 + u8 irq = d->hwirq >> 8;
233 + qpnpint_irq_unmask(d);
236 + qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
239 +static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
241 + struct spmi_pmic_arb_qpnpint_type type;
242 + u8 irq = d->hwirq >> 8;
244 + qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
246 + if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
247 + type.type |= 1 << irq;
248 + if (flow_type & IRQF_TRIGGER_RISING)
249 + type.polarity_high |= 1 << irq;
250 + if (flow_type & IRQF_TRIGGER_FALLING)
251 + type.polarity_low |= 1 << irq;
253 + if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
254 + (flow_type & (IRQF_TRIGGER_LOW)))
257 + type.type &= ~(1 << irq); /* level trig */
258 + if (flow_type & IRQF_TRIGGER_HIGH)
259 + type.polarity_high |= 1 << irq;
261 + type.polarity_low |= 1 << irq;
264 + qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
268 +static struct irq_chip pmic_arb_irqchip = {
269 + .name = "pmic_arb",
270 + .irq_enable = qpnpint_irq_enable,
271 + .irq_ack = qpnpint_irq_ack,
272 + .irq_mask = qpnpint_irq_mask,
273 + .irq_unmask = qpnpint_irq_unmask,
274 + .irq_set_type = qpnpint_irq_set_type,
275 + .flags = IRQCHIP_MASK_ON_SUSPEND
276 + | IRQCHIP_SKIP_SET_WAKE,
279 +struct spmi_pmic_arb_irq_spec {
285 +static int search_mapping_table(struct spmi_pmic_arb_dev *pa,
286 + struct spmi_pmic_arb_irq_spec *spec,
289 + u16 ppid = spec->slave << 8 | spec->per;
290 + u32 *mapping_table = pa->mapping_table;
294 + for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
295 + data = mapping_table[index];
297 + if (ppid & (1 << SPMI_MAPPING_BIT_INDEX(data))) {
298 + if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
299 + index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
301 + *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
305 + if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
306 + index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
308 + *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
317 +static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
318 + struct device_node *controller,
319 + const u32 *intspec,
320 + unsigned int intsize,
321 + unsigned long *out_hwirq,
322 + unsigned int *out_type)
324 + struct spmi_pmic_arb_dev *pa = d->host_data;
325 + struct spmi_pmic_arb_irq_spec spec;
329 + dev_dbg(&pa->spmic->dev,
330 + "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
331 + intspec[0], intspec[1], intspec[2]);
333 + if (d->of_node != controller)
337 + if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
340 + spec.slave = intspec[0];
341 + spec.per = intspec[1];
342 + spec.irq = intspec[2];
344 + err = search_mapping_table(pa, &spec, &apid);
348 + pa->apid_to_ppid[apid] = spec.slave << 8 | spec.per;
350 + /* Keep track of {max,min}_apid for bounding search during interrupt */
351 + if (apid > pa->max_apid)
352 + pa->max_apid = apid;
353 + if (apid < pa->min_apid)
354 + pa->min_apid = apid;
356 + *out_hwirq = spec.slave << 24
360 + *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
362 + dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
367 +static int qpnpint_irq_domain_map(struct irq_domain *d,
369 + irq_hw_number_t hwirq)
371 + struct spmi_pmic_arb_dev *pa = d->host_data;
373 + dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
375 + irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq);
376 + irq_set_chip_data(virq, d->host_data);
377 + irq_set_noprobe(virq);
381 +static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
382 + .map = qpnpint_irq_domain_map,
383 + .xlate = qpnpint_irq_domain_dt_translate,
386 static int spmi_pmic_arb_probe(struct platform_device *pdev)
388 struct spmi_pmic_arb_dev *pa;
389 struct spmi_controller *ctrl;
390 struct resource *res;
395 ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa));
396 @@ -319,6 +642,7 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
399 pa = spmi_controller_get_drvdata(ctrl);
402 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
403 pa->base = devm_ioremap_resource(&ctrl->dev, res);
404 @@ -341,6 +665,12 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
408 + pa->irq = platform_get_irq_byname(pdev, "periph_irq");
414 err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
416 dev_err(&pdev->dev, "channel unspecified.\n");
417 @@ -355,6 +685,29 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
419 pa->channel = channel;
421 + err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
423 + dev_err(&pdev->dev, "EE unspecified.\n");
428 + dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
435 + for (i = 0; i < ARRAY_SIZE(pa->mapping_table); ++i)
436 + pa->mapping_table[i] = readl_relaxed(
437 + pa->cnfg + SPMI_MAPPING_TABLE_REG(i));
439 + /* Initialize max_apid/min_apid to the opposite bounds, during
440 + * the irq domain translation, we are sure to update these */
442 + pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
444 platform_set_drvdata(pdev, ctrl);
445 raw_spin_lock_init(&pa->lock);
447 @@ -362,15 +715,31 @@ static int spmi_pmic_arb_probe(struct platform_device *pdev)
448 ctrl->read_cmd = pmic_arb_read_cmd;
449 ctrl->write_cmd = pmic_arb_write_cmd;
451 + dev_dbg(&pdev->dev, "adding irq domain\n");
452 + pa->domain = irq_domain_add_tree(pdev->dev.of_node,
453 + &pmic_arb_irq_domain_ops, pa);
455 + dev_err(&pdev->dev, "unable to create irq_domain\n");
460 + irq_set_handler_data(pa->irq, pa);
461 + irq_set_chained_handler(pa->irq, pmic_arb_chained_irq);
463 err = spmi_controller_add(ctrl);
466 + goto err_domain_remove;
468 dev_dbg(&ctrl->dev, "PMIC Arb Version 0x%x\n",
469 pmic_arb_base_read(pa, PMIC_ARB_VERSION));
474 + irq_set_chained_handler(pa->irq, NULL);
475 + irq_set_handler_data(pa->irq, NULL);
476 + irq_domain_remove(pa->domain);
478 spmi_controller_put(ctrl);
480 @@ -379,7 +748,11 @@ err_put_ctrl:
481 static int spmi_pmic_arb_remove(struct platform_device *pdev)
483 struct spmi_controller *ctrl = platform_get_drvdata(pdev);
484 + struct spmi_pmic_arb_dev *pa = spmi_controller_get_drvdata(ctrl);
485 spmi_controller_remove(ctrl);
486 + irq_set_chained_handler(pa->irq, NULL);
487 + irq_set_handler_data(pa->irq, NULL);
488 + irq_domain_remove(pa->domain);
489 spmi_controller_put(ctrl);