1 From 24884115a6029995dba2561b1ee810f28a34271a Mon Sep 17 00:00:00 2001
2 From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
3 Date: Thu, 13 Feb 2014 18:21:38 +0200
4 Subject: [PATCH 065/182] spi: Add Qualcomm QUP SPI controller support
6 Qualcomm Universal Peripheral (QUP) core is an AHB slave that
7 provides a common data path (an output FIFO and an input FIFO)
8 for serial peripheral interface (SPI) mini-core. SPI in master
9 mode supports up to 50MHz, up to four chip selects, programmable
10 data path from 4 bits to 32 bits and numerous protocol variants.
12 Cc: Alok Chauhan <alokc@codeaurora.org>
13 Cc: Gilad Avidov <gavidov@codeaurora.org>
14 Cc: Kiran Gunda <kgunda@codeaurora.org>
15 Cc: Sagar Dharia <sdharia@codeaurora.org>
16 Cc: dsneddon@codeaurora.org
17 Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
18 Signed-off-by: Mark Brown <broonie@linaro.org>
20 drivers/spi/Kconfig | 13 +
21 drivers/spi/Makefile | 1 +
22 drivers/spi/spi-qup.c | 837 +++++++++++++++++++++++++++++++++++++++++++++++++
23 3 files changed, 851 insertions(+)
24 create mode 100644 drivers/spi/spi-qup.c
26 --- a/drivers/spi/Kconfig
27 +++ b/drivers/spi/Kconfig
28 @@ -390,6 +390,19 @@ config SPI_RSPI
30 SPI driver for Renesas RSPI and QSPI blocks.
33 + tristate "Qualcomm SPI controller with QUP interface"
34 + depends on ARCH_MSM_DT
36 + Qualcomm Universal Peripheral (QUP) core is an AHB slave that
37 + provides a common data path (an output FIFO and an input FIFO)
38 + for serial peripheral interface (SPI) mini-core. SPI in master
39 + mode supports up to 50MHz, up to four chip selects, programmable
40 + data path from 4 bits to 32 bits and numerous protocol variants.
42 + This driver can also be built as a module. If so, the module
43 + will be called spi_qup.
46 tristate "Samsung S3C24XX series SPI"
47 depends on ARCH_S3C24XX
48 --- a/drivers/spi/Makefile
49 +++ b/drivers/spi/Makefile
50 @@ -60,6 +60,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_
51 spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
52 obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
53 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
54 +obj-$(CONFIG_SPI_QUP) += spi-qup.o
55 obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
56 obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
57 spi-s3c24xx-hw-y := spi-s3c24xx.o
59 +++ b/drivers/spi/spi-qup.c
62 + * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
64 + * This program is free software; you can redistribute it and/or modify
65 + * it under the terms of the GNU General Public License rev 2 and
66 + * only rev 2 as published by the free Software foundation.
68 + * This program is distributed in the hope that it will be useful,
69 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
70 + * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
71 + * GNU General Public License for more details.
74 +#include <linux/clk.h>
75 +#include <linux/delay.h>
76 +#include <linux/err.h>
77 +#include <linux/interrupt.h>
78 +#include <linux/io.h>
79 +#include <linux/list.h>
80 +#include <linux/module.h>
81 +#include <linux/of.h>
82 +#include <linux/platform_device.h>
83 +#include <linux/pm_runtime.h>
84 +#include <linux/spi/spi.h>
86 +#define QUP_CONFIG 0x0000
87 +#define QUP_STATE 0x0004
88 +#define QUP_IO_M_MODES 0x0008
89 +#define QUP_SW_RESET 0x000c
90 +#define QUP_OPERATIONAL 0x0018
91 +#define QUP_ERROR_FLAGS 0x001c
92 +#define QUP_ERROR_FLAGS_EN 0x0020
93 +#define QUP_OPERATIONAL_MASK 0x0028
94 +#define QUP_HW_VERSION 0x0030
95 +#define QUP_MX_OUTPUT_CNT 0x0100
96 +#define QUP_OUTPUT_FIFO 0x0110
97 +#define QUP_MX_WRITE_CNT 0x0150
98 +#define QUP_MX_INPUT_CNT 0x0200
99 +#define QUP_MX_READ_CNT 0x0208
100 +#define QUP_INPUT_FIFO 0x0218
102 +#define SPI_CONFIG 0x0300
103 +#define SPI_IO_CONTROL 0x0304
104 +#define SPI_ERROR_FLAGS 0x0308
105 +#define SPI_ERROR_FLAGS_EN 0x030c
107 +/* QUP_CONFIG fields */
108 +#define QUP_CONFIG_SPI_MODE (1 << 8)
109 +#define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
110 +#define QUP_CONFIG_NO_INPUT BIT(7)
111 +#define QUP_CONFIG_NO_OUTPUT BIT(6)
112 +#define QUP_CONFIG_N 0x001f
114 +/* QUP_STATE fields */
115 +#define QUP_STATE_VALID BIT(2)
116 +#define QUP_STATE_RESET 0
117 +#define QUP_STATE_RUN 1
118 +#define QUP_STATE_PAUSE 3
119 +#define QUP_STATE_MASK 3
120 +#define QUP_STATE_CLEAR 2
122 +#define QUP_HW_VERSION_2_1_1 0x20010001
124 +/* QUP_IO_M_MODES fields */
125 +#define QUP_IO_M_PACK_EN BIT(15)
126 +#define QUP_IO_M_UNPACK_EN BIT(14)
127 +#define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
128 +#define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
129 +#define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
130 +#define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
132 +#define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
133 +#define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
134 +#define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
135 +#define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
137 +#define QUP_IO_M_MODE_FIFO 0
138 +#define QUP_IO_M_MODE_BLOCK 1
139 +#define QUP_IO_M_MODE_DMOV 2
140 +#define QUP_IO_M_MODE_BAM 3
142 +/* QUP_OPERATIONAL fields */
143 +#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
144 +#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
145 +#define QUP_OP_IN_SERVICE_FLAG BIT(9)
146 +#define QUP_OP_OUT_SERVICE_FLAG BIT(8)
147 +#define QUP_OP_IN_FIFO_FULL BIT(7)
148 +#define QUP_OP_OUT_FIFO_FULL BIT(6)
149 +#define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
150 +#define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
152 +/* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
153 +#define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
154 +#define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
155 +#define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
156 +#define QUP_ERROR_INPUT_OVER_RUN BIT(2)
158 +/* SPI_CONFIG fields */
159 +#define SPI_CONFIG_HS_MODE BIT(10)
160 +#define SPI_CONFIG_INPUT_FIRST BIT(9)
161 +#define SPI_CONFIG_LOOPBACK BIT(8)
163 +/* SPI_IO_CONTROL fields */
164 +#define SPI_IO_C_FORCE_CS BIT(11)
165 +#define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
166 +#define SPI_IO_C_MX_CS_MODE BIT(8)
167 +#define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
168 +#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
169 +#define SPI_IO_C_CS_SELECT_MASK 0x000c
170 +#define SPI_IO_C_TRISTATE_CS BIT(1)
171 +#define SPI_IO_C_NO_TRI_STATE BIT(0)
173 +/* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
174 +#define SPI_ERROR_CLK_OVER_RUN BIT(1)
175 +#define SPI_ERROR_CLK_UNDER_RUN BIT(0)
177 +#define SPI_NUM_CHIPSELECTS 4
179 +/* high speed mode is when bus rate is greater then 26MHz */
180 +#define SPI_HS_MIN_RATE 26000000
181 +#define SPI_MAX_RATE 50000000
183 +#define SPI_DELAY_THRESHOLD 1
184 +#define SPI_DELAY_RETRY 10
186 +struct spi_qup_device {
192 + void __iomem *base;
193 + struct device *dev;
194 + struct clk *cclk; /* core clock */
195 + struct clk *iclk; /* interface clock */
205 + struct spi_transfer *xfer;
206 + struct completion done;
208 + int w_size; /* bytes per SPI word */
214 +static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
216 + u32 opstate = readl_relaxed(controller->base + QUP_STATE);
218 + return opstate & QUP_STATE_VALID;
221 +static int spi_qup_set_state(struct spi_qup *controller, u32 state)
223 + unsigned long loop;
227 + while (!spi_qup_is_valid_state(controller)) {
229 + usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
231 + if (++loop > SPI_DELAY_RETRY)
236 + dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
239 + cur_state = readl_relaxed(controller->base + QUP_STATE);
241 + * Per spec: for PAUSE_STATE to RESET_STATE, two writes
242 + * of (b10) are required
244 + if (((cur_state & QUP_STATE_MASK) == QUP_STATE_PAUSE) &&
245 + (state == QUP_STATE_RESET)) {
246 + writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
247 + writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
249 + cur_state &= ~QUP_STATE_MASK;
250 + cur_state |= state;
251 + writel_relaxed(cur_state, controller->base + QUP_STATE);
255 + while (!spi_qup_is_valid_state(controller)) {
257 + usleep_range(SPI_DELAY_THRESHOLD, SPI_DELAY_THRESHOLD * 2);
259 + if (++loop > SPI_DELAY_RETRY)
267 +static void spi_qup_fifo_read(struct spi_qup *controller,
268 + struct spi_transfer *xfer)
270 + u8 *rx_buf = xfer->rx_buf;
272 + int idx, shift, w_size;
274 + w_size = controller->w_size;
276 + while (controller->rx_bytes < xfer->len) {
278 + state = readl_relaxed(controller->base + QUP_OPERATIONAL);
279 + if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
282 + word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
285 + controller->rx_bytes += w_size;
289 + for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {
291 + * The data format depends on bytes per SPI word:
292 + * 4 bytes: 0x12345678
293 + * 2 bytes: 0x00001234
294 + * 1 byte : 0x00000012
296 + shift = BITS_PER_BYTE;
297 + shift *= (w_size - idx - 1);
298 + rx_buf[controller->rx_bytes] = word >> shift;
303 +static void spi_qup_fifo_write(struct spi_qup *controller,
304 + struct spi_transfer *xfer)
306 + const u8 *tx_buf = xfer->tx_buf;
307 + u32 word, state, data;
310 + w_size = controller->w_size;
312 + while (controller->tx_bytes < xfer->len) {
314 + state = readl_relaxed(controller->base + QUP_OPERATIONAL);
315 + if (state & QUP_OP_OUT_FIFO_FULL)
319 + for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
322 + controller->tx_bytes += w_size;
326 + data = tx_buf[controller->tx_bytes];
327 + word |= data << (BITS_PER_BYTE * (3 - idx));
330 + writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
334 +static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
336 + struct spi_qup *controller = dev_id;
337 + struct spi_transfer *xfer;
338 + u32 opflags, qup_err, spi_err;
339 + unsigned long flags;
342 + spin_lock_irqsave(&controller->lock, flags);
343 + xfer = controller->xfer;
344 + controller->xfer = NULL;
345 + spin_unlock_irqrestore(&controller->lock, flags);
347 + qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
348 + spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
349 + opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
351 + writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
352 + writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
353 + writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
356 + dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n",
357 + qup_err, spi_err, opflags);
358 + return IRQ_HANDLED;
362 + if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
363 + dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
364 + if (qup_err & QUP_ERROR_INPUT_UNDER_RUN)
365 + dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
366 + if (qup_err & QUP_ERROR_OUTPUT_UNDER_RUN)
367 + dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
368 + if (qup_err & QUP_ERROR_INPUT_OVER_RUN)
369 + dev_warn(controller->dev, "INPUT_OVER_RUN\n");
375 + if (spi_err & SPI_ERROR_CLK_OVER_RUN)
376 + dev_warn(controller->dev, "CLK_OVER_RUN\n");
377 + if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
378 + dev_warn(controller->dev, "CLK_UNDER_RUN\n");
383 + if (opflags & QUP_OP_IN_SERVICE_FLAG)
384 + spi_qup_fifo_read(controller, xfer);
386 + if (opflags & QUP_OP_OUT_SERVICE_FLAG)
387 + spi_qup_fifo_write(controller, xfer);
389 + spin_lock_irqsave(&controller->lock, flags);
390 + controller->error = error;
391 + controller->xfer = xfer;
392 + spin_unlock_irqrestore(&controller->lock, flags);
394 + if (controller->rx_bytes == xfer->len || error)
395 + complete(&controller->done);
397 + return IRQ_HANDLED;
401 +/* set clock freq ... bits per word */
402 +static int spi_qup_io_config(struct spi_qup *controller,
403 + struct spi_qup_device *chip,
404 + struct spi_transfer *xfer)
406 + u32 config, iomode, mode;
407 + int ret, n_words, w_size;
409 + if (chip->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
410 + dev_err(controller->dev, "too big size for loopback %d > %d\n",
411 + xfer->len, controller->in_fifo_sz);
415 + ret = clk_set_rate(controller->cclk, xfer->speed_hz);
417 + dev_err(controller->dev, "fail to set frequency %d",
422 + if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
423 + dev_err(controller->dev, "cannot set RESET state\n");
428 + if (xfer->bits_per_word <= 8)
430 + else if (xfer->bits_per_word <= 16)
433 + n_words = xfer->len / w_size;
434 + controller->w_size = w_size;
436 + if (n_words <= controller->in_fifo_sz) {
437 + mode = QUP_IO_M_MODE_FIFO;
438 + writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
439 + writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
440 + /* must be zero for FIFO */
441 + writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
442 + writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
444 + mode = QUP_IO_M_MODE_BLOCK;
445 + writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
446 + writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
447 + /* must be zero for BLOCK and BAM */
448 + writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
449 + writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
452 + iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
453 + /* Set input and output transfer mode */
454 + iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
455 + iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
456 + iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
457 + iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
459 + writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
461 + config = readl_relaxed(controller->base + SPI_CONFIG);
463 + if (chip->mode & SPI_LOOP)
464 + config |= SPI_CONFIG_LOOPBACK;
466 + config &= ~SPI_CONFIG_LOOPBACK;
468 + if (chip->mode & SPI_CPHA)
469 + config &= ~SPI_CONFIG_INPUT_FIRST;
471 + config |= SPI_CONFIG_INPUT_FIRST;
474 + * HS_MODE improves signal stability for spi-clk high rates,
475 + * but is invalid in loop back mode.
477 + if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(chip->mode & SPI_LOOP))
478 + config |= SPI_CONFIG_HS_MODE;
480 + config &= ~SPI_CONFIG_HS_MODE;
482 + writel_relaxed(config, controller->base + SPI_CONFIG);
484 + config = readl_relaxed(controller->base + QUP_CONFIG);
485 + config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
486 + config |= xfer->bits_per_word - 1;
487 + config |= QUP_CONFIG_SPI_MODE;
488 + writel_relaxed(config, controller->base + QUP_CONFIG);
490 + writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
494 +static void spi_qup_set_cs(struct spi_device *spi, bool enable)
496 + struct spi_qup *controller = spi_master_get_devdata(spi->master);
497 + struct spi_qup_device *chip = spi_get_ctldata(spi);
499 + u32 iocontol, mask;
501 + iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
503 + /* Disable auto CS toggle and use manual */
504 + iocontol &= ~SPI_IO_C_MX_CS_MODE;
505 + iocontol |= SPI_IO_C_FORCE_CS;
507 + iocontol &= ~SPI_IO_C_CS_SELECT_MASK;
508 + iocontol |= SPI_IO_C_CS_SELECT(chip->select);
510 + mask = SPI_IO_C_CS_N_POLARITY_0 << chip->select;
517 + writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
520 +static int spi_qup_transfer_one(struct spi_master *master,
521 + struct spi_device *spi,
522 + struct spi_transfer *xfer)
524 + struct spi_qup *controller = spi_master_get_devdata(master);
525 + struct spi_qup_device *chip = spi_get_ctldata(spi);
526 + unsigned long timeout, flags;
529 + ret = spi_qup_io_config(controller, chip, xfer);
533 + timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
534 + timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
535 + timeout = 100 * msecs_to_jiffies(timeout);
537 + reinit_completion(&controller->done);
539 + spin_lock_irqsave(&controller->lock, flags);
540 + controller->xfer = xfer;
541 + controller->error = 0;
542 + controller->rx_bytes = 0;
543 + controller->tx_bytes = 0;
544 + spin_unlock_irqrestore(&controller->lock, flags);
546 + if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
547 + dev_warn(controller->dev, "cannot set RUN state\n");
551 + if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
552 + dev_warn(controller->dev, "cannot set PAUSE state\n");
556 + spi_qup_fifo_write(controller, xfer);
558 + if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
559 + dev_warn(controller->dev, "cannot set EXECUTE state\n");
563 + if (!wait_for_completion_timeout(&controller->done, timeout))
566 + spi_qup_set_state(controller, QUP_STATE_RESET);
567 + spin_lock_irqsave(&controller->lock, flags);
568 + controller->xfer = NULL;
570 + ret = controller->error;
571 + spin_unlock_irqrestore(&controller->lock, flags);
575 +static int spi_qup_setup(struct spi_device *spi)
577 + struct spi_qup *controller = spi_master_get_devdata(spi->master);
578 + struct spi_qup_device *chip = spi_get_ctldata(spi);
580 + if (spi->chip_select >= spi->master->num_chipselect) {
581 + dev_err(controller->dev, "invalid chip_select %d\n",
586 + if (spi->max_speed_hz > controller->max_speed_hz) {
587 + dev_err(controller->dev, "invalid max_speed_hz %d\n",
588 + spi->max_speed_hz);
594 + chip = kzalloc(sizeof(*chip), GFP_KERNEL);
596 + dev_err(controller->dev, "no memory for chip data\n");
600 + chip->mode = spi->mode;
601 + chip->select = spi->chip_select;
602 + spi_set_ctldata(spi, chip);
608 +static void spi_qup_cleanup(struct spi_device *spi)
610 + struct spi_qup_device *chip = spi_get_ctldata(spi);
615 + spi_set_ctldata(spi, NULL);
619 +static int spi_qup_probe(struct platform_device *pdev)
621 + struct spi_master *master;
622 + struct clk *iclk, *cclk;
623 + struct spi_qup *controller;
624 + struct resource *res;
625 + struct device *dev;
626 + void __iomem *base;
627 + u32 data, max_freq, iomode;
628 + int ret, irq, size;
631 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
632 + base = devm_ioremap_resource(dev, res);
634 + return PTR_ERR(base);
636 + irq = platform_get_irq(pdev, 0);
641 + cclk = devm_clk_get(dev, "core");
643 + return PTR_ERR(cclk);
645 + iclk = devm_clk_get(dev, "iface");
647 + return PTR_ERR(iclk);
649 + /* This is optional parameter */
650 + if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq))
651 + max_freq = SPI_MAX_RATE;
653 + if (!max_freq || max_freq > SPI_MAX_RATE) {
654 + dev_err(dev, "invalid clock frequency %d\n", max_freq);
658 + ret = clk_prepare_enable(cclk);
660 + dev_err(dev, "cannot enable core clock\n");
664 + ret = clk_prepare_enable(iclk);
666 + clk_disable_unprepare(cclk);
667 + dev_err(dev, "cannot enable iface clock\n");
671 + data = readl_relaxed(base + QUP_HW_VERSION);
673 + if (data < QUP_HW_VERSION_2_1_1) {
674 + clk_disable_unprepare(cclk);
675 + clk_disable_unprepare(iclk);
676 + dev_err(dev, "v.%08x is not supported\n", data);
680 + master = spi_alloc_master(dev, sizeof(struct spi_qup));
682 + clk_disable_unprepare(cclk);
683 + clk_disable_unprepare(iclk);
684 + dev_err(dev, "cannot allocate master\n");
688 + master->bus_num = pdev->id;
689 + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
690 + master->num_chipselect = SPI_NUM_CHIPSELECTS;
691 + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
692 + master->setup = spi_qup_setup;
693 + master->cleanup = spi_qup_cleanup;
694 + master->set_cs = spi_qup_set_cs;
695 + master->transfer_one = spi_qup_transfer_one;
696 + master->dev.of_node = pdev->dev.of_node;
697 + master->auto_runtime_pm = true;
699 + platform_set_drvdata(pdev, master);
701 + controller = spi_master_get_devdata(master);
703 + controller->dev = dev;
704 + controller->base = base;
705 + controller->iclk = iclk;
706 + controller->cclk = cclk;
707 + controller->irq = irq;
708 + controller->max_speed_hz = max_freq;
710 + spin_lock_init(&controller->lock);
711 + init_completion(&controller->done);
713 + iomode = readl_relaxed(base + QUP_IO_M_MODES);
715 + size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode);
717 + controller->out_blk_sz = size * 16;
719 + controller->out_blk_sz = 4;
721 + size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode);
723 + controller->in_blk_sz = size * 16;
725 + controller->in_blk_sz = 4;
727 + size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode);
728 + controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
730 + size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
731 + controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
733 + dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
734 + data, controller->in_blk_sz, controller->in_fifo_sz,
735 + controller->out_blk_sz, controller->out_fifo_sz);
737 + writel_relaxed(1, base + QUP_SW_RESET);
739 + ret = spi_qup_set_state(controller, QUP_STATE_RESET);
741 + dev_err(dev, "cannot set RESET state\n");
745 + writel_relaxed(0, base + QUP_OPERATIONAL);
746 + writel_relaxed(0, base + QUP_IO_M_MODES);
747 + writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
748 + writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
749 + base + SPI_ERROR_FLAGS_EN);
751 + writel_relaxed(0, base + SPI_CONFIG);
752 + writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
754 + ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
755 + IRQF_TRIGGER_HIGH, pdev->name, controller);
759 + ret = devm_spi_register_master(dev, master);
763 + pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
764 + pm_runtime_use_autosuspend(dev);
765 + pm_runtime_set_active(dev);
766 + pm_runtime_enable(dev);
770 + clk_disable_unprepare(cclk);
771 + clk_disable_unprepare(iclk);
772 + spi_master_put(master);
776 +#ifdef CONFIG_PM_RUNTIME
777 +static int spi_qup_pm_suspend_runtime(struct device *device)
779 + struct spi_master *master = dev_get_drvdata(device);
780 + struct spi_qup *controller = spi_master_get_devdata(master);
783 + /* Enable clocks auto gaiting */
784 + config = readl(controller->base + QUP_CONFIG);
785 + config |= QUP_CLOCK_AUTO_GATE;
786 + writel_relaxed(config, controller->base + QUP_CONFIG);
790 +static int spi_qup_pm_resume_runtime(struct device *device)
792 + struct spi_master *master = dev_get_drvdata(device);
793 + struct spi_qup *controller = spi_master_get_devdata(master);
796 + /* Disable clocks auto gaiting */
797 + config = readl_relaxed(controller->base + QUP_CONFIG);
798 + config &= ~QUP_CLOCK_AUTO_GATE;
799 + writel_relaxed(config, controller->base + QUP_CONFIG);
802 +#endif /* CONFIG_PM_RUNTIME */
804 +#ifdef CONFIG_PM_SLEEP
805 +static int spi_qup_suspend(struct device *device)
807 + struct spi_master *master = dev_get_drvdata(device);
808 + struct spi_qup *controller = spi_master_get_devdata(master);
811 + ret = spi_master_suspend(master);
815 + ret = spi_qup_set_state(controller, QUP_STATE_RESET);
819 + clk_disable_unprepare(controller->cclk);
820 + clk_disable_unprepare(controller->iclk);
824 +static int spi_qup_resume(struct device *device)
826 + struct spi_master *master = dev_get_drvdata(device);
827 + struct spi_qup *controller = spi_master_get_devdata(master);
830 + ret = clk_prepare_enable(controller->iclk);
834 + ret = clk_prepare_enable(controller->cclk);
838 + ret = spi_qup_set_state(controller, QUP_STATE_RESET);
842 + return spi_master_resume(master);
844 +#endif /* CONFIG_PM_SLEEP */
846 +static int spi_qup_remove(struct platform_device *pdev)
848 + struct spi_master *master = dev_get_drvdata(&pdev->dev);
849 + struct spi_qup *controller = spi_master_get_devdata(master);
852 + ret = pm_runtime_get_sync(&pdev->dev);
856 + ret = spi_qup_set_state(controller, QUP_STATE_RESET);
860 + clk_disable_unprepare(controller->cclk);
861 + clk_disable_unprepare(controller->iclk);
863 + pm_runtime_put_noidle(&pdev->dev);
864 + pm_runtime_disable(&pdev->dev);
865 + spi_master_put(master);
869 +static struct of_device_id spi_qup_dt_match[] = {
870 + { .compatible = "qcom,spi-qup-v2.1.1", },
871 + { .compatible = "qcom,spi-qup-v2.2.1", },
874 +MODULE_DEVICE_TABLE(of, spi_qup_dt_match);
876 +static const struct dev_pm_ops spi_qup_dev_pm_ops = {
877 + SET_SYSTEM_SLEEP_PM_OPS(spi_qup_suspend, spi_qup_resume)
878 + SET_RUNTIME_PM_OPS(spi_qup_pm_suspend_runtime,
879 + spi_qup_pm_resume_runtime,
883 +static struct platform_driver spi_qup_driver = {
886 + .owner = THIS_MODULE,
887 + .pm = &spi_qup_dev_pm_ops,
888 + .of_match_table = spi_qup_dt_match,
890 + .probe = spi_qup_probe,
891 + .remove = spi_qup_remove,
893 +module_platform_driver(spi_qup_driver);
895 +MODULE_LICENSE("GPL v2");
896 +MODULE_VERSION("0.4");
897 +MODULE_ALIAS("platform:spi_qup");