1 From a8e8c90a3cc81c6a7a44ff7fb18ceb71978c9155 Mon Sep 17 00:00:00 2001
2 From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
3 Date: Thu, 13 Feb 2014 18:21:23 +0200
4 Subject: [PATCH 066/182] spi: qup: Add device tree bindings information
6 The Qualcomm Universal Peripheral (QUP) core is an
7 AHB slave that provides a common data path (an output
8 FIFO and an input FIFO) for serial peripheral interface
11 Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
12 Signed-off-by: Mark Brown <broonie@linaro.org>
14 .../devicetree/bindings/spi/qcom,spi-qup.txt | 85 ++++++++++++++++++++
15 1 file changed, 85 insertions(+)
16 create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
18 diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
20 index 0000000..b82a268
22 +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
24 +Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
26 +The QUP core is an AHB slave that provides a common data path (an output FIFO
27 +and an input FIFO) for serial peripheral interface (SPI) mini-core.
29 +SPI in master mode supports up to 50MHz, up to four chip selects, programmable
30 +data path from 4 bits to 32 bits and numerous protocol variants.
33 +- compatible: Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
34 +- reg: Should contain base register location and length
35 +- interrupts: Interrupt number used by this controller
37 +- clocks: Should contain the core clock and the AHB clock.
38 +- clock-names: Should be "core" for the core clock and "iface" for the
41 +- #address-cells: Number of cells required to define a chip select
42 + address on the SPI bus. Should be set to 1.
43 +- #size-cells: Should be zero.
46 +- spi-max-frequency: Specifies maximum SPI clock frequency,
47 + Units - Hz. Definition as per
48 + Documentation/devicetree/bindings/spi/spi-bus.txt
50 +SPI slave nodes must be children of the SPI master node and can contain
51 +properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
55 + spi_8: spi@f9964000 { /* BLSP2 QUP2 */
57 + compatible = "qcom,spi-qup-v2";
58 + #address-cells = <1>;
60 + reg = <0xf9964000 0x1000>;
61 + interrupts = <0 102 0>;
62 + spi-max-frequency = <19200000>;
64 + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
65 + clock-names = "core", "iface";
67 + pinctrl-names = "default";
68 + pinctrl-0 = <&spi8_default>;
71 + compatible = "arm,pl022-dummy";
72 + #address-cells = <1>;
74 + reg = <0>; /* Chip select 0 */
75 + spi-max-frequency = <19200000>;
80 + compatible = "arm,pl022-dummy";
81 + #address-cells = <1>;
83 + reg = <1>; /* Chip select 1 */
84 + spi-max-frequency = <9600000>;
89 + compatible = "arm,pl022-dummy";
90 + #address-cells = <1>;
92 + reg = <2>; /* Chip select 2 */
93 + spi-max-frequency = <19200000>;
99 + compatible = "arm,pl022-dummy";
100 + #address-cells = <1>;
102 + reg = <3>; /* Chip select 3 */
103 + spi-max-frequency = <19200000>;