1 From 5a58dbf4d82c29f7e6d89abc3520bed1aa2af05c Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Thu, 24 Apr 2014 11:31:20 -0500
4 Subject: [PATCH 088/182] soc: qcom: Add device tree binding for GSBI
6 Add device tree binding support for the QCOM GSBI driver.
8 Signed-off-by: Andy Gross <agross@codeaurora.org>
9 Signed-off-by: Kumar Gala <galak@codeaurora.org>
11 .../devicetree/bindings/soc/qcom/qcom,gsbi.txt | 78 ++++++++++++++++++++
12 include/dt-bindings/soc/qcom,gsbi.h | 26 +++++++
13 2 files changed, 104 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
15 create mode 100644 include/dt-bindings/soc/qcom,gsbi.h
17 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
19 index 0000000..4ce24d4
21 +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
23 +QCOM GSBI (General Serial Bus Interface) Driver
25 +The GSBI controller is modeled as a node with zero or more child nodes, each
26 +representing a serial sub-node device that is mux'd as part of the GSBI
27 +configuration settings. The mode setting will govern the input/output mode of
31 +- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
32 +- reg: Address range for GSBI registers
33 +- clocks: required clock
34 +- clock-names: must contain "iface" entry
35 +- qcom,mode : indicates MUX value for configuration of the serial interface.
36 + Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
39 +- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
40 + dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
42 +Required properties if child node exists:
43 +- #address-cells: Must be 1
44 +- #size-cells: Must be 1
45 +- ranges: Must be present
47 +Properties for children:
49 +A GSBI controller node can contain 0 or more child nodes representing serial
50 +devices. These serial devices can be a QCOM UART, I2C controller, spi
51 +controller, or some combination of aforementioned devices.
53 +See the following for child node definitions:
54 +Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
55 +Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
56 +Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
60 +#include <dt-bindings/soc/qcom,gsbi.h>
63 + compatible = "qcom,gsbi-v1.0.0";
64 + reg = <0x16300000 0x100>;
65 + clocks = <&gcc GSBI4_H_CLK>;
66 + clock-names = "iface";
67 + #address-cells = <1>;
70 + qcom,mode = <GSBI_PROT_I2C_UART>;
71 + qcom,crci = <GSBI_CRCI_QUP>;
73 + /* child nodes go under here */
75 + i2c_qup4: i2c@16380000 {
76 + compatible = "qcom,i2c-qup-v1.1.1";
77 + reg = <0x16380000 0x1000>;
78 + interrupts = <0 153 0>;
80 + clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
81 + clock-names = "core", "iface";
83 + clock-frequency = <200000>;
85 + #address-cells = <1>;
90 + uart4: serial@16340000 {
91 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
92 + reg = <0x16340000 0x1000>,
93 + <0x16300000 0x1000>;
94 + interrupts = <0 152 0x0>;
95 + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
96 + clock-names = "core", "iface";
101 diff --git a/include/dt-bindings/soc/qcom,gsbi.h b/include/dt-bindings/soc/qcom,gsbi.h
103 index 0000000..7ac4292
105 +++ b/include/dt-bindings/soc/qcom,gsbi.h
107 +/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
109 + * This program is free software; you can redistribute it and/or modify
110 + * it under the terms of the GNU General Public License version 2 and
111 + * only version 2 as published by the Free Software Foundation.
113 + * This program is distributed in the hope that it will be useful,
114 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
115 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
116 + * GNU General Public License for more details.
118 +#ifndef __DT_BINDINGS_QCOM_GSBI_H
119 +#define __DT_BINDINGS_QCOM_GSBI_H
121 +#define GSBI_PROT_IDLE 0
122 +#define GSBI_PROT_I2C_UIM 1
123 +#define GSBI_PROT_I2C 2
124 +#define GSBI_PROT_SPI 3
125 +#define GSBI_PROT_UART_W_FC 4
126 +#define GSBI_PROT_UIM 5
127 +#define GSBI_PROT_I2C_UART 6
129 +#define GSBI_CRCI_QUP 0
130 +#define GSBI_CRCI_UART 1