1 From 63495b04141e60ceb40d4632a41b7cd4a3d23dd2 Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Wed, 28 May 2014 12:01:29 -0500
4 Subject: [PATCH 091/182] ARM: dts: qcom: Update msm8974/apq8074 device trees
6 * Move SoC peripherals into an SoC container node
7 * Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
8 * Move spi pinctrl into board file
9 * Cleanup cpu node to match binding spec, enable-method and compatible
10 should be per cpu, not part of the container
11 * Drop interrupts property from l2-cache node as its not part of the
13 * Move timer node out of SoC container
15 Signed-off-by: Kumar Gala <galak@codeaurora.org>
17 arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 +++++++++++++-
18 arch/arm/boot/dts/qcom-msm8974.dtsi | 49 +++++++++---------------
19 2 files changed, 45 insertions(+), 32 deletions(-)
21 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
22 +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
24 model = "Qualcomm APQ8074 Dragonboard";
25 compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
37 cd-gpios = <&msmgpio 62 0x1>;
43 + spi8_default: spi8_default {
46 + function = "blsp_spi8";
50 + function = "blsp_spi8";
54 + function = "blsp_spi8";
58 + function = "blsp_spi8";
64 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
65 +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
69 interrupts = <1 9 0xf04>;
70 - compatible = "qcom,krait";
71 - enable-method = "qcom,kpss-acc-v2";
74 + compatible = "qcom,krait";
75 + enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
83 + compatible = "qcom,krait";
84 + enable-method = "qcom,kpss-acc-v2";
87 next-level-cache = <&L2>;
92 + compatible = "qcom,krait";
93 + enable-method = "qcom,kpss-acc-v2";
96 next-level-cache = <&L2>;
101 + compatible = "qcom,krait";
102 + enable-method = "qcom,kpss-acc-v2";
105 next-level-cache = <&L2>;
108 compatible = "cache";
110 - interrupts = <0 2 0x4>;
111 qcom,saw = <&saw_l2>;
115 interrupts = <1 7 0xf04>;
119 + compatible = "arm,armv7-timer";
120 + interrupts = <1 2 0xf08>,
124 + clock-frequency = <19200000>;
128 #address-cells = <1>;
135 - compatible = "arm,armv7-timer";
136 - interrupts = <1 2 0xf08>,
140 - clock-frequency = <19200000>;
144 #address-cells = <1>;
147 interrupts = <0 108 0x0>;
148 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
149 clock-names = "core", "iface";
150 + status = "disabled";
155 interrupt-controller;
156 #interrupt-cells = <2>;
157 interrupts = <0 208 0>;
159 - spi8_default: spi8_default {
162 - function = "blsp_spi8";
166 - function = "blsp_spi8";
170 - function = "blsp_spi8";
174 - function = "blsp_spi8";