1 From 881200420e6ece87d9abbb13c0653d26455cdbdd Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Wed, 28 May 2014 12:09:53 -0500
4 Subject: [PATCH 092/182] ARM: dts: qcom: Update msm8960 device trees
6 * Move SoC peripherals into an SoC container node
7 * Move serial enabling into board file (qcom-msm8960-cdp.dts)
8 * Cleanup cpu node to match binding spec, enable-method and compatible
9 should be per cpu, not part of the container
10 * Drop interrupts property from l2-cache node as its not part of the
12 * Add GSBI node and configuration of GSBI controller
14 Signed-off-by: Kumar Gala <galak@codeaurora.org>
16 arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++
17 arch/arm/boot/dts/qcom-msm8960.dtsi | 176 ++++++++++++++++++--------------
18 2 files changed, 108 insertions(+), 78 deletions(-)
20 diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
21 index a58fb88..8f75cc4 100644
22 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
23 +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
26 model = "Qualcomm MSM8960 CDP";
27 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
32 + qcom,mode = <GSBI_PROT_I2C_UART>;
39 diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
40 index 997b7b9..5303e53 100644
41 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi
42 +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
44 /include/ "skeleton.dtsi"
46 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
47 +#include <dt-bindings/soc/qcom,gsbi.h>
50 model = "Qualcomm MSM8960";
54 interrupts = <1 14 0x304>;
55 - compatible = "qcom,krait";
56 - enable-method = "qcom,kpss-acc-v1";
59 + compatible = "qcom,krait";
60 + enable-method = "qcom,kpss-acc-v1";
63 next-level-cache = <&L2>;
68 + compatible = "qcom,krait";
69 + enable-method = "qcom,kpss-acc-v1";
72 next-level-cache = <&L2>;
77 - interrupts = <0 2 0x4>;
85 - intc: interrupt-controller@2000000 {
86 - compatible = "qcom,msm-qgic2";
87 - interrupt-controller;
88 - #interrupt-cells = <3>;
89 - reg = < 0x02000000 0x1000 >,
90 - < 0x02002000 0x1000 >;
93 + #address-cells = <1>;
96 + compatible = "simple-bus";
98 + intc: interrupt-controller@2000000 {
99 + compatible = "qcom,msm-qgic2";
100 + interrupt-controller;
101 + #interrupt-cells = <3>;
102 + reg = <0x02000000 0x1000>,
103 + <0x02002000 0x1000>;
107 - compatible = "qcom,kpss-timer", "qcom,msm-timer";
108 - interrupts = <1 1 0x301>,
111 - reg = <0x0200a000 0x100>;
112 - clock-frequency = <27000000>,
114 - cpu-offset = <0x80000>;
117 + compatible = "qcom,kpss-timer", "qcom,msm-timer";
118 + interrupts = <1 1 0x301>,
121 + reg = <0x0200a000 0x100>;
122 + clock-frequency = <27000000>,
124 + cpu-offset = <0x80000>;
127 - msmgpio: gpio@800000 {
128 - compatible = "qcom,msm-gpio";
132 - interrupts = <0 16 0x4>;
133 - interrupt-controller;
134 - #interrupt-cells = <2>;
135 - reg = <0x800000 0x4000>;
137 + msmgpio: gpio@800000 {
138 + compatible = "qcom,msm-gpio";
142 + interrupts = <0 16 0x4>;
143 + interrupt-controller;
144 + #interrupt-cells = <2>;
145 + reg = <0x800000 0x4000>;
148 - gcc: clock-controller@900000 {
149 - compatible = "qcom,gcc-msm8960";
150 - #clock-cells = <1>;
151 - #reset-cells = <1>;
152 - reg = <0x900000 0x4000>;
154 + gcc: clock-controller@900000 {
155 + compatible = "qcom,gcc-msm8960";
156 + #clock-cells = <1>;
157 + #reset-cells = <1>;
158 + reg = <0x900000 0x4000>;
161 - clock-controller@4000000 {
162 - compatible = "qcom,mmcc-msm8960";
163 - reg = <0x4000000 0x1000>;
164 - #clock-cells = <1>;
165 - #reset-cells = <1>;
167 + clock-controller@4000000 {
168 + compatible = "qcom,mmcc-msm8960";
169 + reg = <0x4000000 0x1000>;
170 + #clock-cells = <1>;
171 + #reset-cells = <1>;
174 - acc0: clock-controller@2088000 {
175 - compatible = "qcom,kpss-acc-v1";
176 - reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
178 + acc0: clock-controller@2088000 {
179 + compatible = "qcom,kpss-acc-v1";
180 + reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
183 - acc1: clock-controller@2098000 {
184 - compatible = "qcom,kpss-acc-v1";
185 - reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
187 + acc1: clock-controller@2098000 {
188 + compatible = "qcom,kpss-acc-v1";
189 + reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
192 - saw0: regulator@2089000 {
193 - compatible = "qcom,saw2";
194 - reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
197 + saw0: regulator@2089000 {
198 + compatible = "qcom,saw2";
199 + reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
203 - saw1: regulator@2099000 {
204 - compatible = "qcom,saw2";
205 - reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
208 + saw1: regulator@2099000 {
209 + compatible = "qcom,saw2";
210 + reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
215 - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
216 - reg = <0x16440000 0x1000>,
217 - <0x16400000 0x1000>;
218 - interrupts = <0 154 0x0>;
219 - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
220 - clock-names = "core", "iface";
222 + gsbi5: gsbi@16400000 {
223 + compatible = "qcom,gsbi-v1.0.0";
224 + reg = <0x16400000 0x100>;
225 + clocks = <&gcc GSBI5_H_CLK>;
226 + clock-names = "iface";
227 + #address-cells = <1>;
232 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
233 + reg = <0x16440000 0x1000>,
234 + <0x16400000 0x1000>;
235 + interrupts = <0 154 0x0>;
236 + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
237 + clock-names = "core", "iface";
238 + status = "disabled";
243 - compatible = "qcom,ssbi";
244 - reg = <0x500000 0x1000>;
245 - qcom,controller-type = "pmic-arbiter";
248 + compatible = "qcom,ssbi";
249 + reg = <0x500000 0x1000>;
250 + qcom,controller-type = "pmic-arbiter";
254 - compatible = "qcom,prng";
255 - reg = <0x1a500000 0x200>;
256 - clocks = <&gcc PRNG_CLK>;
257 - clock-names = "core";
259 + compatible = "qcom,prng";
260 + reg = <0x1a500000 0x200>;
261 + clocks = <&gcc PRNG_CLK>;
262 + clock-names = "core";