1 From 881200420e6ece87d9abbb13c0653d26455cdbdd Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Wed, 28 May 2014 12:09:53 -0500
4 Subject: [PATCH 092/182] ARM: dts: qcom: Update msm8960 device trees
6 * Move SoC peripherals into an SoC container node
7 * Move serial enabling into board file (qcom-msm8960-cdp.dts)
8 * Cleanup cpu node to match binding spec, enable-method and compatible
9 should be per cpu, not part of the container
10 * Drop interrupts property from l2-cache node as its not part of the
12 * Add GSBI node and configuration of GSBI controller
14 Signed-off-by: Kumar Gala <galak@codeaurora.org>
16 arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++
17 arch/arm/boot/dts/qcom-msm8960.dtsi | 176 ++++++++++++++++++--------------
18 2 files changed, 108 insertions(+), 78 deletions(-)
20 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
21 +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
24 model = "Qualcomm MSM8960 CDP";
25 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
30 + qcom,mode = <GSBI_PROT_I2C_UART>;
37 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi
38 +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
40 /include/ "skeleton.dtsi"
42 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
43 +#include <dt-bindings/soc/qcom,gsbi.h>
46 model = "Qualcomm MSM8960";
50 interrupts = <1 14 0x304>;
51 - compatible = "qcom,krait";
52 - enable-method = "qcom,kpss-acc-v1";
55 + compatible = "qcom,krait";
56 + enable-method = "qcom,kpss-acc-v1";
59 next-level-cache = <&L2>;
64 + compatible = "qcom,krait";
65 + enable-method = "qcom,kpss-acc-v1";
68 next-level-cache = <&L2>;
73 - interrupts = <0 2 0x4>;
81 - intc: interrupt-controller@2000000 {
82 - compatible = "qcom,msm-qgic2";
83 - interrupt-controller;
84 - #interrupt-cells = <3>;
85 - reg = < 0x02000000 0x1000 >,
86 - < 0x02002000 0x1000 >;
89 + #address-cells = <1>;
92 + compatible = "simple-bus";
94 + intc: interrupt-controller@2000000 {
95 + compatible = "qcom,msm-qgic2";
96 + interrupt-controller;
97 + #interrupt-cells = <3>;
98 + reg = <0x02000000 0x1000>,
99 + <0x02002000 0x1000>;
103 - compatible = "qcom,kpss-timer", "qcom,msm-timer";
104 - interrupts = <1 1 0x301>,
107 - reg = <0x0200a000 0x100>;
108 - clock-frequency = <27000000>,
110 - cpu-offset = <0x80000>;
113 + compatible = "qcom,kpss-timer", "qcom,msm-timer";
114 + interrupts = <1 1 0x301>,
117 + reg = <0x0200a000 0x100>;
118 + clock-frequency = <27000000>,
120 + cpu-offset = <0x80000>;
123 - msmgpio: gpio@800000 {
124 - compatible = "qcom,msm-gpio";
128 - interrupts = <0 16 0x4>;
129 - interrupt-controller;
130 - #interrupt-cells = <2>;
131 - reg = <0x800000 0x4000>;
133 + msmgpio: gpio@800000 {
134 + compatible = "qcom,msm-gpio";
138 + interrupts = <0 16 0x4>;
139 + interrupt-controller;
140 + #interrupt-cells = <2>;
141 + reg = <0x800000 0x4000>;
144 - gcc: clock-controller@900000 {
145 - compatible = "qcom,gcc-msm8960";
146 - #clock-cells = <1>;
147 - #reset-cells = <1>;
148 - reg = <0x900000 0x4000>;
150 + gcc: clock-controller@900000 {
151 + compatible = "qcom,gcc-msm8960";
152 + #clock-cells = <1>;
153 + #reset-cells = <1>;
154 + reg = <0x900000 0x4000>;
157 - clock-controller@4000000 {
158 - compatible = "qcom,mmcc-msm8960";
159 - reg = <0x4000000 0x1000>;
160 - #clock-cells = <1>;
161 - #reset-cells = <1>;
163 + clock-controller@4000000 {
164 + compatible = "qcom,mmcc-msm8960";
165 + reg = <0x4000000 0x1000>;
166 + #clock-cells = <1>;
167 + #reset-cells = <1>;
170 - acc0: clock-controller@2088000 {
171 - compatible = "qcom,kpss-acc-v1";
172 - reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
174 + acc0: clock-controller@2088000 {
175 + compatible = "qcom,kpss-acc-v1";
176 + reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
179 - acc1: clock-controller@2098000 {
180 - compatible = "qcom,kpss-acc-v1";
181 - reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
183 + acc1: clock-controller@2098000 {
184 + compatible = "qcom,kpss-acc-v1";
185 + reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
188 - saw0: regulator@2089000 {
189 - compatible = "qcom,saw2";
190 - reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
193 + saw0: regulator@2089000 {
194 + compatible = "qcom,saw2";
195 + reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
199 - saw1: regulator@2099000 {
200 - compatible = "qcom,saw2";
201 - reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
204 + saw1: regulator@2099000 {
205 + compatible = "qcom,saw2";
206 + reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
211 - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
212 - reg = <0x16440000 0x1000>,
213 - <0x16400000 0x1000>;
214 - interrupts = <0 154 0x0>;
215 - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
216 - clock-names = "core", "iface";
218 + gsbi5: gsbi@16400000 {
219 + compatible = "qcom,gsbi-v1.0.0";
220 + reg = <0x16400000 0x100>;
221 + clocks = <&gcc GSBI5_H_CLK>;
222 + clock-names = "iface";
223 + #address-cells = <1>;
228 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
229 + reg = <0x16440000 0x1000>,
230 + <0x16400000 0x1000>;
231 + interrupts = <0 154 0x0>;
232 + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
233 + clock-names = "core", "iface";
234 + status = "disabled";
239 - compatible = "qcom,ssbi";
240 - reg = <0x500000 0x1000>;
241 - qcom,controller-type = "pmic-arbiter";
244 + compatible = "qcom,ssbi";
245 + reg = <0x500000 0x1000>;
246 + qcom,controller-type = "pmic-arbiter";
250 - compatible = "qcom,prng";
251 - reg = <0x1a500000 0x200>;
252 - clocks = <&gcc PRNG_CLK>;
253 - clock-names = "core";
255 + compatible = "qcom,prng";
256 + reg = <0x1a500000 0x200>;
257 + clocks = <&gcc PRNG_CLK>;
258 + clock-names = "core";