target/linux/ipq806x/patches/0096-ARM-dts-qcom-Add-APQ8084-SoC-support.patch

   1 From 8c52931421759b70fc37771be3390813a2a2f9f5 Mon Sep 17 00:00:00 2001
   2 From: Georgi Djakov <gdjakov@mm-sol.com>
   3 Date: Fri, 23 May 2014 18:12:29 +0300
   4 Subject: [PATCH 096/182] ARM: dts: qcom: Add APQ8084 SoC support
   5
   6 Add support for the Qualcomm Snapdragon 805 APQ8084 SoC. It is
   7 used on APQ8084-MTP and other boards.
   8
   9 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
  10 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  11 ---
  12  arch/arm/boot/dts/qcom-apq8084.dtsi |  179 +++++++++++++++++++++++++++++++++++
  13  arch/arm/mach-qcom/board.c          |    1 +
  14  2 files changed, 180 insertions(+)
  15  create mode 100644 arch/arm/boot/dts/qcom-apq8084.dtsi
  16
  17 diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
  18 new file mode 100644
  19 index 0000000..e3e009a
  20 --- /dev/null
  21 +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
  22 @@ -0,0 +1,179 @@
  23 +/dts-v1/;
  24 +
  25 +#include "skeleton.dtsi"
  26 +
  27 +/ {
  28 +       model = "Qualcomm APQ 8084";
  29 +       compatible = "qcom,apq8084";
  30 +       interrupt-parent = <&intc>;
  31 +
  32 +       cpus {
  33 +               #address-cells = <1>;
  34 +               #size-cells = <0>;
  35 +
  36 +               cpu@0 {
  37 +                       device_type = "cpu";
  38 +                       compatible = "qcom,krait";
  39 +                       reg = <0>;
  40 +                       enable-method = "qcom,kpss-acc-v2";
  41 +                       next-level-cache = <&L2>;
  42 +                       qcom,acc = <&acc0>;
  43 +               };
  44 +
  45 +               cpu@1 {
  46 +                       device_type = "cpu";
  47 +                       compatible = "qcom,krait";
  48 +                       reg = <1>;
  49 +                       enable-method = "qcom,kpss-acc-v2";
  50 +                       next-level-cache = <&L2>;
  51 +                       qcom,acc = <&acc1>;
  52 +               };
  53 +
  54 +               cpu@2 {
  55 +                       device_type = "cpu";
  56 +                       compatible = "qcom,krait";
  57 +                       reg = <2>;
  58 +                       enable-method = "qcom,kpss-acc-v2";
  59 +                       next-level-cache = <&L2>;
  60 +                       qcom,acc = <&acc2>;
  61 +               };
  62 +
  63 +               cpu@3 {
  64 +                       device_type = "cpu";
  65 +                       compatible = "qcom,krait";
  66 +                       reg = <3>;
  67 +                       enable-method = "qcom,kpss-acc-v2";
  68 +                       next-level-cache = <&L2>;
  69 +                       qcom,acc = <&acc3>;
  70 +               };
  71 +
  72 +               L2: l2-cache {
  73 +                       compatible = "qcom,arch-cache";
  74 +                       cache-level = <2>;
  75 +                       qcom,saw = <&saw_l2>;
  76 +               };
  77 +       };
  78 +
  79 +       cpu-pmu {
  80 +               compatible = "qcom,krait-pmu";
  81 +               interrupts = <1 7 0xf04>;
  82 +       };
  83 +
  84 +       timer {
  85 +               compatible = "arm,armv7-timer";
  86 +               interrupts = <1 2 0xf08>,
  87 +                            <1 3 0xf08>,
  88 +                            <1 4 0xf08>,
  89 +                            <1 1 0xf08>;
  90 +               clock-frequency = <19200000>;
  91 +       };
  92 +
  93 +       soc: soc {
  94 +               #address-cells = <1>;
  95 +               #size-cells = <1>;
  96 +               ranges;
  97 +               compatible = "simple-bus";
  98 +
  99 +               intc: interrupt-controller@f9000000 {
 100 +                       compatible = "qcom,msm-qgic2";
 101 +                       interrupt-controller;
 102 +                       #interrupt-cells = <3>;
 103 +                       reg = <0xf9000000 0x1000>,
 104 +                             <0xf9002000 0x1000>;
 105 +               };
 106 +
 107 +               timer@f9020000 {
 108 +                       #address-cells = <1>;
 109 +                       #size-cells = <1>;
 110 +                       ranges;
 111 +                       compatible = "arm,armv7-timer-mem";
 112 +                       reg = <0xf9020000 0x1000>;
 113 +                       clock-frequency = <19200000>;
 114 +
 115 +                       frame@f9021000 {
 116 +                               frame-number = <0>;
 117 +                               interrupts = <0 8 0x4>,
 118 +                                            <0 7 0x4>;
 119 +                               reg = <0xf9021000 0x1000>,
 120 +                                     <0xf9022000 0x1000>;
 121 +                       };
 122 +
 123 +                       frame@f9023000 {
 124 +                               frame-number = <1>;
 125 +                               interrupts = <0 9 0x4>;
 126 +                               reg = <0xf9023000 0x1000>;
 127 +                               status = "disabled";
 128 +                       };
 129 +
 130 +                       frame@f9024000 {
 131 +                               frame-number = <2>;
 132 +                               interrupts = <0 10 0x4>;
 133 +                               reg = <0xf9024000 0x1000>;
 134 +                               status = "disabled";
 135 +                       };
 136 +
 137 +                       frame@f9025000 {
 138 +                               frame-number = <3>;
 139 +                               interrupts = <0 11 0x4>;
 140 +                               reg = <0xf9025000 0x1000>;
 141 +                               status = "disabled";
 142 +                       };
 143 +
 144 +                       frame@f9026000 {
 145 +                               frame-number = <4>;
 146 +                               interrupts = <0 12 0x4>;
 147 +                               reg = <0xf9026000 0x1000>;
 148 +                               status = "disabled";
 149 +                       };
 150 +
 151 +                       frame@f9027000 {
 152 +                               frame-number = <5>;
 153 +                               interrupts = <0 13 0x4>;
 154 +                               reg = <0xf9027000 0x1000>;
 155 +                               status = "disabled";
 156 +                       };
 157 +
 158 +                       frame@f9028000 {
 159 +                               frame-number = <6>;
 160 +                               interrupts = <0 14 0x4>;
 161 +                               reg = <0xf9028000 0x1000>;
 162 +                               status = "disabled";
 163 +                       };
 164 +               };
 165 +
 166 +               saw_l2: regulator@f9012000 {
 167 +                       compatible = "qcom,saw2";
 168 +                       reg = <0xf9012000 0x1000>;
 169 +                       regulator;
 170 +               };
 171 +
 172 +               acc0: clock-controller@f9088000 {
 173 +                       compatible = "qcom,kpss-acc-v2";
 174 +                       reg = <0xf9088000 0x1000>,
 175 +                             <0xf9008000 0x1000>;
 176 +               };
 177 +
 178 +               acc1: clock-controller@f9098000 {
 179 +                       compatible = "qcom,kpss-acc-v2";
 180 +                       reg = <0xf9098000 0x1000>,
 181 +                             <0xf9008000 0x1000>;
 182 +               };
 183 +
 184 +               acc2: clock-controller@f90a8000 {
 185 +                       compatible = "qcom,kpss-acc-v2";
 186 +                       reg = <0xf90a8000 0x1000>,
 187 +                             <0xf9008000 0x1000>;
 188 +               };
 189 +
 190 +               acc3: clock-controller@f90b8000 {
 191 +                       compatible = "qcom,kpss-acc-v2";
 192 +                       reg = <0xf90b8000 0x1000>,
 193 +                             <0xf9008000 0x1000>;
 194 +               };
 195 +
 196 +               restart@fc4ab000 {
 197 +                       compatible = "qcom,pshold";
 198 +                       reg = <0xfc4ab000 0x4>;
 199 +               };
 200 +       };
 201 +};
 202 diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
 203 index 350fa8d..c437a99 100644
 204 --- a/arch/arm/mach-qcom/board.c
 205 +++ b/arch/arm/mach-qcom/board.c
 206 @@ -17,6 +17,7 @@
 207  static const char * const qcom_dt_match[] __initconst = {
 208         "qcom,apq8064",
 209         "qcom,apq8074-dragonboard",
 210 +       "qcom,apq8084",
 211         "qcom,msm8660-surf",
 212         "qcom,msm8960-cdp",
 213         NULL
 214 --
 215 1.7.10.4
 216