1 From 8c52931421759b70fc37771be3390813a2a2f9f5 Mon Sep 17 00:00:00 2001
2 From: Georgi Djakov <gdjakov@mm-sol.com>
3 Date: Fri, 23 May 2014 18:12:29 +0300
4 Subject: [PATCH 096/182] ARM: dts: qcom: Add APQ8084 SoC support
6 Add support for the Qualcomm Snapdragon 805 APQ8084 SoC. It is
7 used on APQ8084-MTP and other boards.
9 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
10 Signed-off-by: Kumar Gala <galak@codeaurora.org>
12 arch/arm/boot/dts/qcom-apq8084.dtsi | 179 +++++++++++++++++++++++++++++++++++
13 arch/arm/mach-qcom/board.c | 1 +
14 2 files changed, 180 insertions(+)
15 create mode 100644 arch/arm/boot/dts/qcom-apq8084.dtsi
17 diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
19 index 0000000..e3e009a
21 +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
25 +#include "skeleton.dtsi"
28 + model = "Qualcomm APQ 8084";
29 + compatible = "qcom,apq8084";
30 + interrupt-parent = <&intc>;
33 + #address-cells = <1>;
37 + device_type = "cpu";
38 + compatible = "qcom,krait";
40 + enable-method = "qcom,kpss-acc-v2";
41 + next-level-cache = <&L2>;
46 + device_type = "cpu";
47 + compatible = "qcom,krait";
49 + enable-method = "qcom,kpss-acc-v2";
50 + next-level-cache = <&L2>;
55 + device_type = "cpu";
56 + compatible = "qcom,krait";
58 + enable-method = "qcom,kpss-acc-v2";
59 + next-level-cache = <&L2>;
64 + device_type = "cpu";
65 + compatible = "qcom,krait";
67 + enable-method = "qcom,kpss-acc-v2";
68 + next-level-cache = <&L2>;
73 + compatible = "qcom,arch-cache";
75 + qcom,saw = <&saw_l2>;
80 + compatible = "qcom,krait-pmu";
81 + interrupts = <1 7 0xf04>;
85 + compatible = "arm,armv7-timer";
86 + interrupts = <1 2 0xf08>,
90 + clock-frequency = <19200000>;
94 + #address-cells = <1>;
97 + compatible = "simple-bus";
99 + intc: interrupt-controller@f9000000 {
100 + compatible = "qcom,msm-qgic2";
101 + interrupt-controller;
102 + #interrupt-cells = <3>;
103 + reg = <0xf9000000 0x1000>,
104 + <0xf9002000 0x1000>;
108 + #address-cells = <1>;
111 + compatible = "arm,armv7-timer-mem";
112 + reg = <0xf9020000 0x1000>;
113 + clock-frequency = <19200000>;
116 + frame-number = <0>;
117 + interrupts = <0 8 0x4>,
119 + reg = <0xf9021000 0x1000>,
120 + <0xf9022000 0x1000>;
124 + frame-number = <1>;
125 + interrupts = <0 9 0x4>;
126 + reg = <0xf9023000 0x1000>;
127 + status = "disabled";
131 + frame-number = <2>;
132 + interrupts = <0 10 0x4>;
133 + reg = <0xf9024000 0x1000>;
134 + status = "disabled";
138 + frame-number = <3>;
139 + interrupts = <0 11 0x4>;
140 + reg = <0xf9025000 0x1000>;
141 + status = "disabled";
145 + frame-number = <4>;
146 + interrupts = <0 12 0x4>;
147 + reg = <0xf9026000 0x1000>;
148 + status = "disabled";
152 + frame-number = <5>;
153 + interrupts = <0 13 0x4>;
154 + reg = <0xf9027000 0x1000>;
155 + status = "disabled";
159 + frame-number = <6>;
160 + interrupts = <0 14 0x4>;
161 + reg = <0xf9028000 0x1000>;
162 + status = "disabled";
166 + saw_l2: regulator@f9012000 {
167 + compatible = "qcom,saw2";
168 + reg = <0xf9012000 0x1000>;
172 + acc0: clock-controller@f9088000 {
173 + compatible = "qcom,kpss-acc-v2";
174 + reg = <0xf9088000 0x1000>,
175 + <0xf9008000 0x1000>;
178 + acc1: clock-controller@f9098000 {
179 + compatible = "qcom,kpss-acc-v2";
180 + reg = <0xf9098000 0x1000>,
181 + <0xf9008000 0x1000>;
184 + acc2: clock-controller@f90a8000 {
185 + compatible = "qcom,kpss-acc-v2";
186 + reg = <0xf90a8000 0x1000>,
187 + <0xf9008000 0x1000>;
190 + acc3: clock-controller@f90b8000 {
191 + compatible = "qcom,kpss-acc-v2";
192 + reg = <0xf90b8000 0x1000>,
193 + <0xf9008000 0x1000>;
197 + compatible = "qcom,pshold";
198 + reg = <0xfc4ab000 0x4>;
202 diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
203 index 350fa8d..c437a99 100644
204 --- a/arch/arm/mach-qcom/board.c
205 +++ b/arch/arm/mach-qcom/board.c
207 static const char * const qcom_dt_match[] __initconst = {
209 "qcom,apq8074-dragonboard",