1 From 3123079878e29eb8c541111e30de4d1bb42ac6f9 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Fri, 16 May 2014 16:07:11 -0700
4 Subject: [PATCH 105/182] clk: qcom: Support display RCG clocks
6 Add support for the DSI/EDP/HDMI RCG clocks. With the proper
7 display driver in place this should allow us to support display
8 clocks on msm8974 based devices.
10 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
11 Signed-off-by: Mike Turquette <mturquette@linaro.org>
13 drivers/clk/qcom/clk-rcg.h | 3 +
14 drivers/clk/qcom/clk-rcg2.c | 299 ++++++++++++++++++++++++++++++++++++++++---
15 2 files changed, 287 insertions(+), 15 deletions(-)
17 diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
18 index 1d6b6de..b9ec11d 100644
19 --- a/drivers/clk/qcom/clk-rcg.h
20 +++ b/drivers/clk/qcom/clk-rcg.h
21 @@ -155,5 +155,8 @@ struct clk_rcg2 {
22 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
24 extern const struct clk_ops clk_rcg2_ops;
25 +extern const struct clk_ops clk_edp_pixel_ops;
26 +extern const struct clk_ops clk_byte_ops;
27 +extern const struct clk_ops clk_pixel_ops;
30 diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
31 index cbecaec..cd185d5 100644
32 --- a/drivers/clk/qcom/clk-rcg2.c
33 +++ b/drivers/clk/qcom/clk-rcg2.c
35 #include <linux/clk-provider.h>
36 #include <linux/delay.h>
37 #include <linux/regmap.h>
38 +#include <linux/math64.h>
40 #include <asm/div64.h>
42 @@ -225,31 +226,25 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
43 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
46 -static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
47 +static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
49 - struct clk_rcg2 *rcg = to_clk_rcg2(hw);
50 - const struct freq_tbl *f;
54 - f = find_freq(rcg->freq_tbl, rate);
58 if (rcg->mnd_width && f->n) {
59 mask = BIT(rcg->mnd_width) - 1;
60 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG,
62 + ret = regmap_update_bits(rcg->clkr.regmap,
63 + rcg->cmd_rcgr + M_REG, mask, f->m);
67 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG,
68 - mask, ~(f->n - f->m));
69 + ret = regmap_update_bits(rcg->clkr.regmap,
70 + rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
74 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + D_REG,
76 + ret = regmap_update_bits(rcg->clkr.regmap,
77 + rcg->cmd_rcgr + D_REG, mask, ~f->n);
81 @@ -260,14 +255,26 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
82 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
83 if (rcg->mnd_width && f->n)
84 cfg |= CFG_MODE_DUAL_EDGE;
85 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask,
87 + ret = regmap_update_bits(rcg->clkr.regmap,
88 + rcg->cmd_rcgr + CFG_REG, mask, cfg);
92 return update_config(rcg);
95 +static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
97 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
98 + const struct freq_tbl *f;
100 + f = find_freq(rcg->freq_tbl, rate);
104 + return clk_rcg2_configure(rcg, f);
107 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
108 unsigned long parent_rate)
110 @@ -290,3 +297,265 @@ const struct clk_ops clk_rcg2_ops = {
111 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
113 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
120 +static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
121 + { 52, 295 }, /* 119 M */
122 + { 11, 57 }, /* 130.25 M */
123 + { 63, 307 }, /* 138.50 M */
124 + { 11, 50 }, /* 148.50 M */
125 + { 47, 206 }, /* 154 M */
126 + { 31, 100 }, /* 205.25 M */
127 + { 107, 269 }, /* 268.50 M */
131 +static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
132 + { 31, 211 }, /* 119 M */
133 + { 32, 199 }, /* 130.25 M */
134 + { 63, 307 }, /* 138.50 M */
135 + { 11, 60 }, /* 148.50 M */
136 + { 50, 263 }, /* 154 M */
137 + { 31, 120 }, /* 205.25 M */
138 + { 119, 359 }, /* 268.50 M */
142 +static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
143 + unsigned long parent_rate)
145 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
146 + struct freq_tbl f = *rcg->freq_tbl;
147 + const struct frac_entry *frac;
148 + int delta = 100000;
149 + s64 src_rate = parent_rate;
151 + u32 mask = BIT(rcg->hid_width) - 1;
154 + if (src_rate == 810000000)
155 + frac = frac_table_810m;
157 + frac = frac_table_675m;
159 + for (; frac->num; frac++) {
161 + request *= frac->den;
162 + request = div_s64(request, frac->num);
163 + if ((src_rate < (request - delta)) ||
164 + (src_rate > (request + delta)))
167 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
169 + f.pre_div = hid_div;
170 + f.pre_div >>= CFG_SRC_DIV_SHIFT;
175 + return clk_rcg2_configure(rcg, &f);
181 +static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
182 + unsigned long rate, unsigned long parent_rate, u8 index)
184 + /* Parent index is set statically in frequency table */
185 + return clk_edp_pixel_set_rate(hw, rate, parent_rate);
188 +static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
189 + unsigned long *p_rate, struct clk **p)
191 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
192 + const struct freq_tbl *f = rcg->freq_tbl;
193 + const struct frac_entry *frac;
194 + int delta = 100000;
195 + s64 src_rate = *p_rate;
197 + u32 mask = BIT(rcg->hid_width) - 1;
200 + /* Force the correct parent */
201 + *p = clk_get_parent_by_index(hw->clk, f->src);
203 + if (src_rate == 810000000)
204 + frac = frac_table_810m;
206 + frac = frac_table_675m;
208 + for (; frac->num; frac++) {
210 + request *= frac->den;
211 + request = div_s64(request, frac->num);
212 + if ((src_rate < (request - delta)) ||
213 + (src_rate > (request + delta)))
216 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
218 + hid_div >>= CFG_SRC_DIV_SHIFT;
221 + return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
228 +const struct clk_ops clk_edp_pixel_ops = {
229 + .is_enabled = clk_rcg2_is_enabled,
230 + .get_parent = clk_rcg2_get_parent,
231 + .set_parent = clk_rcg2_set_parent,
232 + .recalc_rate = clk_rcg2_recalc_rate,
233 + .set_rate = clk_edp_pixel_set_rate,
234 + .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
235 + .determine_rate = clk_edp_pixel_determine_rate,
237 +EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
239 +static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
240 + unsigned long *p_rate, struct clk **p)
242 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
243 + const struct freq_tbl *f = rcg->freq_tbl;
244 + unsigned long parent_rate, div;
245 + u32 mask = BIT(rcg->hid_width) - 1;
250 + *p = clk_get_parent_by_index(hw->clk, f->src);
251 + *p_rate = parent_rate = __clk_round_rate(*p, rate);
253 + div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
254 + div = min_t(u32, div, mask);
256 + return calc_rate(parent_rate, 0, 0, 0, div);
259 +static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
260 + unsigned long parent_rate)
262 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
263 + struct freq_tbl f = *rcg->freq_tbl;
265 + u32 mask = BIT(rcg->hid_width) - 1;
267 + div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
268 + div = min_t(u32, div, mask);
272 + return clk_rcg2_configure(rcg, &f);
275 +static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
276 + unsigned long rate, unsigned long parent_rate, u8 index)
278 + /* Parent index is set statically in frequency table */
279 + return clk_byte_set_rate(hw, rate, parent_rate);
282 +const struct clk_ops clk_byte_ops = {
283 + .is_enabled = clk_rcg2_is_enabled,
284 + .get_parent = clk_rcg2_get_parent,
285 + .set_parent = clk_rcg2_set_parent,
286 + .recalc_rate = clk_rcg2_recalc_rate,
287 + .set_rate = clk_byte_set_rate,
288 + .set_rate_and_parent = clk_byte_set_rate_and_parent,
289 + .determine_rate = clk_byte_determine_rate,
291 +EXPORT_SYMBOL_GPL(clk_byte_ops);
293 +static const struct frac_entry frac_table_pixel[] = {
301 +static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
302 + unsigned long *p_rate, struct clk **p)
304 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
305 + unsigned long request, src_rate;
306 + int delta = 100000;
307 + const struct freq_tbl *f = rcg->freq_tbl;
308 + const struct frac_entry *frac = frac_table_pixel;
309 + struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
311 + for (; frac->num; frac++) {
312 + request = (rate * frac->den) / frac->num;
314 + src_rate = __clk_round_rate(parent, request);
315 + if ((src_rate < (request - delta)) ||
316 + (src_rate > (request + delta)))
319 + *p_rate = src_rate;
320 + return (src_rate * frac->num) / frac->den;
326 +static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
327 + unsigned long parent_rate)
329 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
330 + struct freq_tbl f = *rcg->freq_tbl;
331 + const struct frac_entry *frac = frac_table_pixel;
332 + unsigned long request, src_rate;
333 + int delta = 100000;
334 + u32 mask = BIT(rcg->hid_width) - 1;
336 + struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
338 + for (; frac->num; frac++) {
339 + request = (rate * frac->den) / frac->num;
341 + src_rate = __clk_round_rate(parent, request);
342 + if ((src_rate < (request - delta)) ||
343 + (src_rate > (request + delta)))
346 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
348 + f.pre_div = hid_div;
349 + f.pre_div >>= CFG_SRC_DIV_SHIFT;
354 + return clk_rcg2_configure(rcg, &f);
359 +static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
360 + unsigned long parent_rate, u8 index)
362 + /* Parent index is set statically in frequency table */
363 + return clk_pixel_set_rate(hw, rate, parent_rate);
366 +const struct clk_ops clk_pixel_ops = {
367 + .is_enabled = clk_rcg2_is_enabled,
368 + .get_parent = clk_rcg2_get_parent,
369 + .set_parent = clk_rcg2_set_parent,
370 + .recalc_rate = clk_rcg2_recalc_rate,
371 + .set_rate = clk_pixel_set_rate,
372 + .set_rate_and_parent = clk_pixel_set_rate_and_parent,
373 + .determine_rate = clk_pixel_determine_rate,
375 +EXPORT_SYMBOL_GPL(clk_pixel_ops);