1 From fd06a2cc719296f65a280cb1533b125f63cfcb34 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Mon, 28 Apr 2014 15:58:11 -0700
4 Subject: [PATCH 127/182] clk: qcom: Add support for setting rates on PLLs
6 Some PLLs may require changing their rate at runtime. Add support
9 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
11 drivers/clk/qcom/clk-pll.c | 68 +++++++++++++++++++++++++++++++++++++++++++-
12 drivers/clk/qcom/clk-pll.h | 20 +++++++++++++
13 2 files changed, 87 insertions(+), 1 deletion(-)
15 diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
16 index 0f927c5..80c7a76 100644
17 --- a/drivers/clk/qcom/clk-pll.c
18 +++ b/drivers/clk/qcom/clk-pll.c
19 @@ -97,7 +97,7 @@ static unsigned long
20 clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
22 struct clk_pll *pll = to_clk_pll(hw);
24 + u32 l, m, n, config;
28 @@ -116,13 +116,79 @@ clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
32 + if (pll->post_div_width) {
33 + regmap_read(pll->clkr.regmap, pll->config_reg, &config);
34 + config >>= pll->post_div_shift;
35 + config &= BIT(pll->post_div_width) - 1;
43 +struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
48 + for (; f->freq; f++)
49 + if (rate <= f->freq)
56 +clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
57 + unsigned long *p_rate, struct clk **p)
59 + struct clk_pll *pll = to_clk_pll(hw);
60 + const struct pll_freq_tbl *f;
62 + f = find_freq(pll->freq_tbl, rate);
64 + return clk_pll_recalc_rate(hw, *p_rate);
70 +clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
72 + struct clk_pll *pll = to_clk_pll(hw);
73 + const struct pll_freq_tbl *f;
76 + u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
78 + f = find_freq(pll->freq_tbl, rate);
82 + regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
83 + enabled = (mode & enable_mask) == enable_mask;
86 + clk_pll_disable(hw);
88 + regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
89 + regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
90 + regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
91 + regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
99 const struct clk_ops clk_pll_ops = {
100 .enable = clk_pll_enable,
101 .disable = clk_pll_disable,
102 .recalc_rate = clk_pll_recalc_rate,
103 + .determine_rate = clk_pll_determine_rate,
104 + .set_rate = clk_pll_set_rate,
106 EXPORT_SYMBOL_GPL(clk_pll_ops);
108 diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
109 index 0775a99..5f9928b 100644
110 --- a/drivers/clk/qcom/clk-pll.h
111 +++ b/drivers/clk/qcom/clk-pll.h
113 #include "clk-regmap.h"
116 + * struct pll_freq_tbl - PLL frequency table
120 + * @ibits: internal values
122 +struct pll_freq_tbl {
123 + unsigned long freq;
131 * struct clk_pll - phase locked loop (PLL)
135 * @mode_reg: mode register
136 * @status_reg: status register
137 * @status_bit: ANDed with @status_reg to determine if PLL is enabled
138 + * @freq_tbl: PLL frequency table
139 * @hw: handle between common and hardware-specific interfaces
142 @@ -36,6 +52,10 @@ struct clk_pll {
149 + const struct pll_freq_tbl *freq_tbl;
151 struct clk_regmap clkr;