1 From 856324d2daa3246ac62d7920d6a274e1fa35bcf5 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Mon, 28 Apr 2014 15:59:16 -0700
4 Subject: [PATCH 128/182] clk: qcom: Add support for banked MD RCGs
6 The banked MD RCGs in global clock control have a different
7 register layout than the ones implemented in multimedia clock
8 control. Add support for these types of clocks so we can change
9 the rates of the UBI32 clocks.
11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
13 drivers/clk/qcom/clk-rcg.c | 99 ++++++++++++++++++++-------------------
14 drivers/clk/qcom/clk-rcg.h | 5 +-
15 drivers/clk/qcom/mmcc-msm8960.c | 24 +++++++---
16 3 files changed, 73 insertions(+), 55 deletions(-)
18 diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
19 index abfc2b6..7bce729 100644
20 --- a/drivers/clk/qcom/clk-rcg.c
21 +++ b/drivers/clk/qcom/clk-rcg.c
22 @@ -67,16 +67,16 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
24 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
25 int num_parents = __clk_get_num_parents(hw->clk);
32 - regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
33 - bank = reg_to_bank(rcg, ctl);
34 + regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
35 + bank = reg_to_bank(rcg, reg);
38 - regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
39 + regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
40 ns = ns_to_src(s, ns);
42 for (i = 0; i < num_parents; i++)
43 @@ -192,90 +192,93 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
45 static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
47 - u32 ns, md, ctl, *regp;
57 bool banked_mn = !!rcg->mn[1].width;
58 + bool banked_p = !!rcg->p[1].pre_div_width;
59 struct clk_hw *hw = &rcg->clkr.hw;
61 enabled = __clk_is_enabled(hw->clk);
63 - regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
64 - regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
68 - bank_reg = rcg->clkr.enable_reg;
71 - bank_reg = rcg->ns_reg;
74 - bank = reg_to_bank(rcg, *regp);
75 + regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
76 + bank = reg_to_bank(rcg, reg);
77 new_bank = enabled ? !bank : bank;
79 + ns_reg = rcg->ns_reg[new_bank];
80 + regmap_read(rcg->clkr.regmap, ns_reg, &ns);
83 mn = &rcg->mn[new_bank];
84 md_reg = rcg->md_reg[new_bank];
86 ns |= BIT(mn->mnctr_reset_bit);
87 - regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
88 + regmap_write(rcg->clkr.regmap, ns_reg, ns);
90 regmap_read(rcg->clkr.regmap, md_reg, &md);
91 md = mn_to_md(mn, f->m, f->n, md);
92 regmap_write(rcg->clkr.regmap, md_reg, md);
94 ns = mn_to_ns(mn, f->m, f->n, ns);
95 - regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
96 + regmap_write(rcg->clkr.regmap, ns_reg, ns);
98 - ctl = mn_to_reg(mn, f->m, f->n, ctl);
99 - regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
100 + /* Two NS registers means mode control is in NS register */
101 + if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
102 + ns = mn_to_reg(mn, f->m, f->n, ns);
103 + regmap_write(rcg->clkr.regmap, ns_reg, ns);
105 + reg = mn_to_reg(mn, f->m, f->n, reg);
106 + regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
109 ns &= ~BIT(mn->mnctr_reset_bit);
110 - regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
112 + regmap_write(rcg->clkr.regmap, ns_reg, ns);
116 p = &rcg->p[new_bank];
117 ns = pre_div_to_ns(p, f->pre_div - 1, ns);
120 s = &rcg->s[new_bank];
121 ns = src_to_ns(s, s->parent_map[f->src], ns);
122 - regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
123 + regmap_write(rcg->clkr.regmap, ns_reg, ns);
126 - *regp ^= BIT(rcg->mux_sel_bit);
127 - regmap_write(rcg->clkr.regmap, bank_reg, *regp);
128 + regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
129 + reg ^= BIT(rcg->mux_sel_bit);
130 + regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
134 static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
136 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
137 - u32 ns, ctl, md, reg;
140 struct freq_tbl f = { 0 };
141 bool banked_mn = !!rcg->mn[1].width;
142 + bool banked_p = !!rcg->p[1].pre_div_width;
144 - regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
145 - regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
146 - reg = banked_mn ? ctl : ns;
148 + regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
149 bank = reg_to_bank(rcg, reg);
151 + regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
154 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
155 f.m = md_to_m(&rcg->mn[bank], md);
156 f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
158 - f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
163 + f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
166 configure_bank(rcg, &f);
169 @@ -336,28 +339,30 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
170 u32 m, n, pre_div, ns, md, mode, reg;
173 + bool banked_p = !!rcg->p[1].pre_div_width;
174 bool banked_mn = !!rcg->mn[1].width;
176 - regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
179 - regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, ®);
183 + regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
184 bank = reg_to_bank(rcg, reg);
186 + regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
187 + m = n = pre_div = mode = 0;
191 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
193 n = ns_m_to_n(mn, ns, m);
194 + /* Two NS registers means mode control is in NS register */
195 + if (rcg->ns_reg[0] != rcg->ns_reg[1])
197 mode = reg_to_mnctr_mode(mn, reg);
198 - return calc_rate(parent_rate, m, n, mode, 0);
200 - pre_div = ns_to_pre_div(&rcg->p[bank], ns);
201 - return calc_rate(parent_rate, 0, 0, 0, pre_div);
205 + pre_div = ns_to_pre_div(&rcg->p[bank], ns);
207 + return calc_rate(parent_rate, m, n, mode, pre_div);
211 diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
212 index b9ec11d..5f8b06d 100644
213 --- a/drivers/clk/qcom/clk-rcg.h
214 +++ b/drivers/clk/qcom/clk-rcg.h
215 @@ -102,7 +102,7 @@ extern const struct clk_ops clk_rcg_ops;
216 * struct clk_dyn_rcg - root clock generator with glitch free mux
218 * @mux_sel_bit: bit to switch glitch free mux
219 - * @ns_reg: NS register
220 + * @ns_reg: NS0 and NS1 register
221 * @md_reg: MD0 and MD1 register
222 * @mn: mn counter (banked)
223 * @s: source selector (banked)
224 @@ -112,8 +112,9 @@ extern const struct clk_ops clk_rcg_ops;
235 diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
236 index 12f3c0b..ce48ad1 100644
237 --- a/drivers/clk/qcom/mmcc-msm8960.c
238 +++ b/drivers/clk/qcom/mmcc-msm8960.c
239 @@ -726,9 +726,11 @@ static struct freq_tbl clk_tbl_gfx2d[] = {
242 static struct clk_dyn_rcg gfx2d0_src = {
244 + .ns_reg[0] = 0x0070,
245 + .ns_reg[1] = 0x0070,
248 + .bank_reg = 0x0060,
251 .mnctr_reset_bit = 25,
252 @@ -784,9 +786,11 @@ static struct clk_branch gfx2d0_clk = {
255 static struct clk_dyn_rcg gfx2d1_src = {
257 + .ns_reg[0] = 0x007c,
258 + .ns_reg[1] = 0x007c,
261 + .bank_reg = 0x0074,
264 .mnctr_reset_bit = 25,
265 @@ -862,9 +866,11 @@ static struct freq_tbl clk_tbl_gfx3d[] = {
268 static struct clk_dyn_rcg gfx3d_src = {
270 + .ns_reg[0] = 0x008c,
271 + .ns_reg[1] = 0x008c,
274 + .bank_reg = 0x0080,
277 .mnctr_reset_bit = 25,
278 @@ -1051,9 +1057,11 @@ static struct freq_tbl clk_tbl_mdp[] = {
281 static struct clk_dyn_rcg mdp_src = {
283 + .ns_reg[0] = 0x00d0,
284 + .ns_reg[1] = 0x00d0,
287 + .bank_reg = 0x00c0,
290 .mnctr_reset_bit = 31,
291 @@ -1158,7 +1166,9 @@ static struct freq_tbl clk_tbl_rot[] = {
294 static struct clk_dyn_rcg rot_src = {
296 + .ns_reg[0] = 0x00e8,
297 + .ns_reg[1] = 0x00e8,
298 + .bank_reg = 0x00e8,
302 @@ -1355,9 +1365,11 @@ static struct freq_tbl clk_tbl_vcodec[] = {
305 static struct clk_dyn_rcg vcodec_src = {
307 + .ns_reg[0] = 0x0100,
308 + .ns_reg[1] = 0x0100,
311 + .bank_reg = 0x00f8,
314 .mnctr_reset_bit = 31,