target/linux/ipq806x/patches/0130-ARM-qcom-Add-initial-IPQ8064-SoC-and-AP148-device-tr.patch

   1 From 1c6e51ffb10f5bf93a3018c7c1e04d7ed93f944e Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Fri, 7 Mar 2014 10:56:59 -0600
   4 Subject: [PATCH 130/182] ARM: qcom: Add initial IPQ8064 SoC and AP148 device
   5  trees
   6
   7 Add basic IPQ8064 SoC include device tree and support for basic booting on
   8 the AP148 Reference board.
   9
  10 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  11 ---
  12  arch/arm/boot/dts/Makefile               |    1 +
  13  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   25 +++++
  14  arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi |    1 +
  15  arch/arm/boot/dts/qcom-ipq8064.dtsi      |  176 ++++++++++++++++++++++++++++++
  16  arch/arm/mach-qcom/board.c               |    2 +
  17  5 files changed, 205 insertions(+)
  18  create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  19  create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
  20  create mode 100644 arch/arm/boot/dts/qcom-ipq8064.dtsi
  21
  22 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
  23 index f2aeb95..f22c51d 100644
  24 --- a/arch/arm/boot/dts/Makefile
  25 +++ b/arch/arm/boot/dts/Makefile
  26 @@ -235,6 +235,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
  27         qcom-apq8064-ifc6410.dtb \
  28         qcom-apq8074-dragonboard.dtb \
  29         qcom-apq8084-mtp.dtb \
  30 +       qcom-ipq8064-ap148.dtb \
  31         qcom-msm8660-surf.dtb \
  32         qcom-msm8960-cdp.dtb
  33  dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
  34 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  35 new file mode 100644
  36 index 0000000..100b6eb
  37 --- /dev/null
  38 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  39 @@ -0,0 +1,25 @@
  40 +#include "qcom-ipq8064-v1.0.dtsi"
  41 +
  42 +/ {
  43 +       model = "Qualcomm IPQ8064/AP148";
  44 +       compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
  45 +
  46 +       reserved-memory {
  47 +               #address-cells = <1>;
  48 +               #size-cells = <1>;
  49 +               rsvd@41200000 {
  50 +                       reg = <0x41200000 0x300000>;
  51 +                       no-map;
  52 +               };
  53 +       };
  54 +
  55 +       soc {
  56 +               gsbi@16300000 {
  57 +                       qcom,mode = <GSBI_PROT_I2C_UART>;
  58 +                       status = "ok";
  59 +                       serial@16340000 {
  60 +                               status = "ok";
  61 +                       };
  62 +               };
  63 +       };
  64 +};
  65 diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
  66 new file mode 100644
  67 index 0000000..7093b07
  68 --- /dev/null
  69 +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
  70 @@ -0,0 +1 @@
  71 +#include "qcom-ipq8064.dtsi"
  72 diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  73 new file mode 100644
  74 index 0000000..952afb7
  75 --- /dev/null
  76 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  77 @@ -0,0 +1,176 @@
  78 +/dts-v1/;
  79 +
  80 +#include "skeleton.dtsi"
  81 +#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
  82 +#include <dt-bindings/soc/qcom,gsbi.h>
  83 +
  84 +/ {
  85 +       model = "Qualcomm IPQ8064";
  86 +       compatible = "qcom,ipq8064";
  87 +       interrupt-parent = <&intc>;
  88 +
  89 +       cpus {
  90 +               #address-cells = <1>;
  91 +               #size-cells = <0>;
  92 +
  93 +               cpu@0 {
  94 +                       compatible = "qcom,krait";
  95 +                       enable-method = "qcom,kpss-acc-v1";
  96 +                       device_type = "cpu";
  97 +                       reg = <0>;
  98 +                       next-level-cache = <&L2>;
  99 +                       qcom,acc = <&acc0>;
 100 +                       qcom,saw = <&saw0>;
 101 +               };
 102 +
 103 +               cpu@1 {
 104 +                       compatible = "qcom,krait";
 105 +                       enable-method = "qcom,kpss-acc-v1";
 106 +                       device_type = "cpu";
 107 +                       reg = <1>;
 108 +                       next-level-cache = <&L2>;
 109 +                       qcom,acc = <&acc1>;
 110 +                       qcom,saw = <&saw1>;
 111 +               };
 112 +
 113 +               L2: l2-cache {
 114 +                       compatible = "cache";
 115 +                       cache-level = <2>;
 116 +               };
 117 +       };
 118 +
 119 +       cpu-pmu {
 120 +               compatible = "qcom,krait-pmu";
 121 +               interrupts = <1 10 0x304>;
 122 +       };
 123 +
 124 +       reserved-memory {
 125 +               #address-cells = <1>;
 126 +               #size-cells = <1>;
 127 +               ranges;
 128 +
 129 +               nss@40000000 {
 130 +                       reg = <0x40000000 0x1000000>;
 131 +                       no-map;
 132 +               };
 133 +
 134 +               smem@41000000 {
 135 +                       reg = <0x41000000 0x200000>;
 136 +                       no-map;
 137 +               };
 138 +       };
 139 +
 140 +       soc: soc {
 141 +               #address-cells = <1>;
 142 +               #size-cells = <1>;
 143 +               ranges;
 144 +               compatible = "simple-bus";
 145 +
 146 +               qcom_pinmux: pinmux@800000 {
 147 +                       compatible = "qcom,ipq8064-pinctrl";
 148 +                       reg = <0x800000 0x4000>;
 149 +
 150 +                       gpio-controller;
 151 +                       #gpio-cells = <2>;
 152 +                       interrupt-controller;
 153 +                       #interrupt-cells = <2>;
 154 +                       interrupts = <0 32 0x4>;
 155 +               };
 156 +
 157 +               intc: interrupt-controller@2000000 {
 158 +                       compatible = "qcom,msm-qgic2";
 159 +                       interrupt-controller;
 160 +                       #interrupt-cells = <3>;
 161 +                       reg = <0x02000000 0x1000>,
 162 +                             <0x02002000 0x1000>;
 163 +               };
 164 +
 165 +               timer@200a000 {
 166 +                       compatible = "qcom,kpss-timer", "qcom,msm-timer";
 167 +                       interrupts = <1 1 0x301>,
 168 +                                    <1 2 0x301>,
 169 +                                    <1 3 0x301>;
 170 +                       reg = <0x0200a000 0x100>;
 171 +                       clock-frequency = <25000000>,
 172 +                                         <32768>;
 173 +                       cpu-offset = <0x80000>;
 174 +               };
 175 +
 176 +               acc0: clock-controller@2088000 {
 177 +                       compatible = "qcom,kpss-acc-v1";
 178 +                       reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 179 +               };
 180 +
 181 +               acc1: clock-controller@2098000 {
 182 +                       compatible = "qcom,kpss-acc-v1";
 183 +                       reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 184 +               };
 185 +
 186 +               saw0: regulator@2089000 {
 187 +                       compatible = "qcom,saw2";
 188 +                       reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 189 +                       regulator;
 190 +               };
 191 +
 192 +               saw1: regulator@2099000 {
 193 +                       compatible = "qcom,saw2";
 194 +                       reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 195 +                       regulator;
 196 +               };
 197 +
 198 +               gsbi2: gsbi@12480000 {
 199 +                       compatible = "qcom,gsbi-v1.0.0";
 200 +                       reg = <0x12480000 0x100>;
 201 +                       clocks = <&gcc GSBI2_H_CLK>;
 202 +                       clock-names = "iface";
 203 +                       #address-cells = <1>;
 204 +                       #size-cells = <1>;
 205 +                       ranges;
 206 +                       status = "disabled";
 207 +
 208 +                       serial@12490000 {
 209 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 210 +                               reg = <0x12490000 0x1000>,
 211 +                                     <0x12480000 0x1000>;
 212 +                               interrupts = <0 195 0x0>;
 213 +                               clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
 214 +                               clock-names = "core", "iface";
 215 +                               status = "disabled";
 216 +                       };
 217 +               };
 218 +
 219 +               gsbi4: gsbi@16300000 {
 220 +                       compatible = "qcom,gsbi-v1.0.0";
 221 +                       reg = <0x16300000 0x100>;
 222 +                       clocks = <&gcc GSBI4_H_CLK>;
 223 +                       clock-names = "iface";
 224 +                       #address-cells = <1>;
 225 +                       #size-cells = <1>;
 226 +                       ranges;
 227 +                       status = "disabled";
 228 +
 229 +                       serial@16340000 {
 230 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 231 +                               reg = <0x16340000 0x1000>,
 232 +                                     <0x16300000 0x1000>;
 233 +                               interrupts = <0 152 0x0>;
 234 +                               clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
 235 +                               clock-names = "core", "iface";
 236 +                               status = "disabled";
 237 +                       };
 238 +               };
 239 +
 240 +               qcom,ssbi@500000 {
 241 +                       compatible = "qcom,ssbi";
 242 +                       reg = <0x00500000 0x1000>;
 243 +                       qcom,controller-type = "pmic-arbiter";
 244 +               };
 245 +
 246 +               gcc: clock-controller@900000 {
 247 +                       compatible = "qcom,gcc-ipq8064";
 248 +                       reg = <0x00900000 0x4000>;
 249 +                       #clock-cells = <1>;
 250 +                       #reset-cells = <1>;
 251 +               };
 252 +       };
 253 +};
 254 diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
 255 index c437a99..6d8bbf7 100644
 256 --- a/arch/arm/mach-qcom/board.c
 257 +++ b/arch/arm/mach-qcom/board.c
 258 @@ -18,6 +18,8 @@ static const char * const qcom_dt_match[] __initconst = {
 259         "qcom,apq8064",
 260         "qcom,apq8074-dragonboard",
 261         "qcom,apq8084",
 262 +       "qcom,ipq8062",
 263 +       "qcom,ipq8064",
 264         "qcom,msm8660-surf",
 265         "qcom,msm8960-cdp",
 266         NULL
 267 --
 268 1.7.10.4
 269