1 From 1c6e51ffb10f5bf93a3018c7c1e04d7ed93f944e Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Fri, 7 Mar 2014 10:56:59 -0600
4 Subject: [PATCH 130/182] ARM: qcom: Add initial IPQ8064 SoC and AP148 device
7 Add basic IPQ8064 SoC include device tree and support for basic booting on
8 the AP148 Reference board.
10 Signed-off-by: Kumar Gala <galak@codeaurora.org>
12 arch/arm/boot/dts/Makefile | 1 +
13 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 25 +++++
14 arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 1 +
15 arch/arm/boot/dts/qcom-ipq8064.dtsi | 176 ++++++++++++++++++++++++++++++
16 arch/arm/mach-qcom/board.c | 2 +
17 5 files changed, 205 insertions(+)
18 create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap148.dts
19 create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
20 create mode 100644 arch/arm/boot/dts/qcom-ipq8064.dtsi
22 --- a/arch/arm/boot/dts/Makefile
23 +++ b/arch/arm/boot/dts/Makefile
24 @@ -235,6 +235,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
25 qcom-apq8064-ifc6410.dtb \
26 qcom-apq8074-dragonboard.dtb \
27 qcom-apq8084-mtp.dtb \
28 + qcom-ipq8064-ap148.dtb \
29 qcom-msm8660-surf.dtb \
31 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
33 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
35 +#include "qcom-ipq8064-v1.0.dtsi"
38 + model = "Qualcomm IPQ8064/AP148";
39 + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
42 + #address-cells = <1>;
45 + reg = <0x41200000 0x300000>;
52 + qcom,mode = <GSBI_PROT_I2C_UART>;
61 +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
63 +#include "qcom-ipq8064.dtsi"
65 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
69 +#include "skeleton.dtsi"
70 +#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
71 +#include <dt-bindings/soc/qcom,gsbi.h>
74 + model = "Qualcomm IPQ8064";
75 + compatible = "qcom,ipq8064";
76 + interrupt-parent = <&intc>;
79 + #address-cells = <1>;
83 + compatible = "qcom,krait";
84 + enable-method = "qcom,kpss-acc-v1";
85 + device_type = "cpu";
87 + next-level-cache = <&L2>;
93 + compatible = "qcom,krait";
94 + enable-method = "qcom,kpss-acc-v1";
95 + device_type = "cpu";
97 + next-level-cache = <&L2>;
103 + compatible = "cache";
109 + compatible = "qcom,krait-pmu";
110 + interrupts = <1 10 0x304>;
114 + #address-cells = <1>;
119 + reg = <0x40000000 0x1000000>;
124 + reg = <0x41000000 0x200000>;
130 + #address-cells = <1>;
133 + compatible = "simple-bus";
135 + qcom_pinmux: pinmux@800000 {
136 + compatible = "qcom,ipq8064-pinctrl";
137 + reg = <0x800000 0x4000>;
141 + interrupt-controller;
142 + #interrupt-cells = <2>;
143 + interrupts = <0 32 0x4>;
146 + intc: interrupt-controller@2000000 {
147 + compatible = "qcom,msm-qgic2";
148 + interrupt-controller;
149 + #interrupt-cells = <3>;
150 + reg = <0x02000000 0x1000>,
151 + <0x02002000 0x1000>;
155 + compatible = "qcom,kpss-timer", "qcom,msm-timer";
156 + interrupts = <1 1 0x301>,
159 + reg = <0x0200a000 0x100>;
160 + clock-frequency = <25000000>,
162 + cpu-offset = <0x80000>;
165 + acc0: clock-controller@2088000 {
166 + compatible = "qcom,kpss-acc-v1";
167 + reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
170 + acc1: clock-controller@2098000 {
171 + compatible = "qcom,kpss-acc-v1";
172 + reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
175 + saw0: regulator@2089000 {
176 + compatible = "qcom,saw2";
177 + reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
181 + saw1: regulator@2099000 {
182 + compatible = "qcom,saw2";
183 + reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
187 + gsbi2: gsbi@12480000 {
188 + compatible = "qcom,gsbi-v1.0.0";
189 + reg = <0x12480000 0x100>;
190 + clocks = <&gcc GSBI2_H_CLK>;
191 + clock-names = "iface";
192 + #address-cells = <1>;
195 + status = "disabled";
198 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
199 + reg = <0x12490000 0x1000>,
200 + <0x12480000 0x1000>;
201 + interrupts = <0 195 0x0>;
202 + clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
203 + clock-names = "core", "iface";
204 + status = "disabled";
208 + gsbi4: gsbi@16300000 {
209 + compatible = "qcom,gsbi-v1.0.0";
210 + reg = <0x16300000 0x100>;
211 + clocks = <&gcc GSBI4_H_CLK>;
212 + clock-names = "iface";
213 + #address-cells = <1>;
216 + status = "disabled";
219 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
220 + reg = <0x16340000 0x1000>,
221 + <0x16300000 0x1000>;
222 + interrupts = <0 152 0x0>;
223 + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
224 + clock-names = "core", "iface";
225 + status = "disabled";
230 + compatible = "qcom,ssbi";
231 + reg = <0x00500000 0x1000>;
232 + qcom,controller-type = "pmic-arbiter";
235 + gcc: clock-controller@900000 {
236 + compatible = "qcom,gcc-ipq8064";
237 + reg = <0x00900000 0x4000>;
238 + #clock-cells = <1>;
239 + #reset-cells = <1>;
243 --- a/arch/arm/mach-qcom/board.c
244 +++ b/arch/arm/mach-qcom/board.c
245 @@ -18,6 +18,8 @@ static const char * const qcom_dt_match[
247 "qcom,apq8074-dragonboard",